1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2da3363d5SSimon Glass /* 3da3363d5SSimon Glass * Copyright (C) 2011 The Chromium Authors 4da3363d5SSimon Glass */ 5da3363d5SSimon Glass 6da3363d5SSimon Glass #include <common.h> 7da3363d5SSimon Glass #include <dm.h> 8da3363d5SSimon Glass #include <asm/io.h> 9da3363d5SSimon Glass #include <asm/arch/iomap.h> 10da3363d5SSimon Glass #include <asm/arch/pch.h> 11da3363d5SSimon Glass 12da3363d5SSimon Glass static int broadwell_northbridge_early_init(struct udevice *dev) 13da3363d5SSimon Glass { 14da3363d5SSimon Glass /* Move earlier? */ 15da3363d5SSimon Glass dm_pci_write_config32(dev, PCIEXBAR + 4, 0); 16da3363d5SSimon Glass /* 64MiB - 0-63 buses */ 17da3363d5SSimon Glass dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); 18da3363d5SSimon Glass 19da3363d5SSimon Glass dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 20da3363d5SSimon Glass dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1); 21da3363d5SSimon Glass dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1); 22da3363d5SSimon Glass writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR); 23da3363d5SSimon Glass writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR); 24da3363d5SSimon Glass 25da3363d5SSimon Glass /* Set C0000-FFFFF to access RAM on both reads and writes */ 26da3363d5SSimon Glass dm_pci_write_config8(dev, PAM0, 0x30); 27da3363d5SSimon Glass dm_pci_write_config8(dev, PAM1, 0x33); 28da3363d5SSimon Glass dm_pci_write_config8(dev, PAM2, 0x33); 29da3363d5SSimon Glass dm_pci_write_config8(dev, PAM3, 0x33); 30da3363d5SSimon Glass dm_pci_write_config8(dev, PAM4, 0x33); 31da3363d5SSimon Glass dm_pci_write_config8(dev, PAM5, 0x33); 32da3363d5SSimon Glass dm_pci_write_config8(dev, PAM6, 0x33); 33da3363d5SSimon Glass 34da3363d5SSimon Glass /* Device enable: IGD and Mini-HD */ 35da3363d5SSimon Glass dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); 36da3363d5SSimon Glass 37da3363d5SSimon Glass return 0; 38da3363d5SSimon Glass } 39da3363d5SSimon Glass 40da3363d5SSimon Glass static int broadwell_northbridge_probe(struct udevice *dev) 41da3363d5SSimon Glass { 42da3363d5SSimon Glass if (!(gd->flags & GD_FLG_RELOC)) 43da3363d5SSimon Glass return broadwell_northbridge_early_init(dev); 44da3363d5SSimon Glass 45da3363d5SSimon Glass return 0; 46da3363d5SSimon Glass } 47da3363d5SSimon Glass 48da3363d5SSimon Glass static const struct udevice_id broadwell_northbridge_ids[] = { 49da3363d5SSimon Glass { .compatible = "intel,broadwell-northbridge" }, 50da3363d5SSimon Glass { } 51da3363d5SSimon Glass }; 52da3363d5SSimon Glass 53da3363d5SSimon Glass U_BOOT_DRIVER(broadwell_northbridge_drv) = { 54da3363d5SSimon Glass .name = "broadwell_northbridge", 55da3363d5SSimon Glass .id = UCLASS_NORTHBRIDGE, 56da3363d5SSimon Glass .of_match = broadwell_northbridge_ids, 57da3363d5SSimon Glass .probe = broadwell_northbridge_probe, 58da3363d5SSimon Glass }; 59