1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 Google, Inc 4 * 5 * Based on code from coreboot src/soc/intel/broadwell/me_status.c 6 */ 7 8 #include <common.h> 9 #include <errno.h> 10 #include <asm/arch/me.h> 11 12 static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset) 13 { 14 u32 dword; 15 16 dm_pci_read_config32(dev, offset, &dword); 17 memcpy(ptr, &dword, sizeof(dword)); 18 } 19 20 int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp, 21 uint16_t *checksump) 22 { 23 int count; 24 u32 hsiover; 25 struct me_hfs hfs; 26 27 /* Query for HSIO version, overloads H_GS and HFS */ 28 dm_pci_write_config32(dev, PCI_ME_H_GS, 29 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); 30 31 /* Must wait for ME acknowledgement */ 32 for (count = ME_RETRY; count > 0; --count) { 33 me_read_dword_ptr(dev, &hfs, PCI_ME_HFS); 34 if (hfs.bios_msg_ack) 35 break; 36 udelay(ME_DELAY); 37 } 38 if (!count) { 39 debug("ERROR: ME failed to respond\n"); 40 return -ETIMEDOUT; 41 } 42 43 /* HSIO version should be in HFS_5 */ 44 dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover); 45 *versionp = hsiover >> 16; 46 *checksump = hsiover & 0xffff; 47 48 debug("ME: HSIO Version : %d (CRC 0x%04x)\n", 49 *versionp, *checksump); 50 51 /* Reset registers to normal behavior */ 52 dm_pci_write_config32(dev, PCI_ME_H_GS, 53 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); 54 55 return 0; 56 } 57