1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Based on code from coreboot src/soc/intel/broadwell/me_status.c 7 */ 8 9 #include <common.h> 10 #include <errno.h> 11 #include <asm/arch/me.h> 12 13 static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset) 14 { 15 u32 dword; 16 17 dm_pci_read_config32(dev, offset, &dword); 18 memcpy(ptr, &dword, sizeof(dword)); 19 } 20 21 int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp, 22 uint16_t *checksump) 23 { 24 int count; 25 u32 hsiover; 26 struct me_hfs hfs; 27 28 /* Query for HSIO version, overloads H_GS and HFS */ 29 dm_pci_write_config32(dev, PCI_ME_H_GS, 30 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); 31 32 /* Must wait for ME acknowledgement */ 33 for (count = ME_RETRY; count > 0; --count) { 34 me_read_dword_ptr(dev, &hfs, PCI_ME_HFS); 35 if (hfs.bios_msg_ack) 36 break; 37 udelay(ME_DELAY); 38 } 39 if (!count) { 40 debug("ERROR: ME failed to respond\n"); 41 return -ETIMEDOUT; 42 } 43 44 /* HSIO version should be in HFS_5 */ 45 dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover); 46 *versionp = hsiover >> 16; 47 *checksump = hsiover & 0xffff; 48 49 debug("ME: HSIO Version : %d (CRC 0x%04x)\n", 50 *versionp, *checksump); 51 52 /* Reset registers to normal behavior */ 53 dm_pci_write_config32(dev, PCI_ME_H_GS, 54 ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER); 55 56 return 0; 57 } 58