1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Based on code from coreboot src/soc/intel/broadwell/cpu.c 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <cpu.h> 12 #include <asm/cpu.h> 13 #include <asm/cpu_x86.h> 14 #include <asm/cpu_common.h> 15 #include <asm/intel_regs.h> 16 #include <asm/msr.h> 17 #include <asm/post.h> 18 #include <asm/turbo.h> 19 #include <asm/arch/cpu.h> 20 #include <asm/arch/pch.h> 21 #include <asm/arch/rcb.h> 22 23 struct cpu_broadwell_priv { 24 bool ht_disabled; 25 }; 26 27 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ 28 static const u8 power_limit_time_sec_to_msr[] = { 29 [0] = 0x00, 30 [1] = 0x0a, 31 [2] = 0x0b, 32 [3] = 0x4b, 33 [4] = 0x0c, 34 [5] = 0x2c, 35 [6] = 0x4c, 36 [7] = 0x6c, 37 [8] = 0x0d, 38 [10] = 0x2d, 39 [12] = 0x4d, 40 [14] = 0x6d, 41 [16] = 0x0e, 42 [20] = 0x2e, 43 [24] = 0x4e, 44 [28] = 0x6e, 45 [32] = 0x0f, 46 [40] = 0x2f, 47 [48] = 0x4f, 48 [56] = 0x6f, 49 [64] = 0x10, 50 [80] = 0x30, 51 [96] = 0x50, 52 [112] = 0x70, 53 [128] = 0x11, 54 }; 55 56 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ 57 static const u8 power_limit_time_msr_to_sec[] = { 58 [0x00] = 0, 59 [0x0a] = 1, 60 [0x0b] = 2, 61 [0x4b] = 3, 62 [0x0c] = 4, 63 [0x2c] = 5, 64 [0x4c] = 6, 65 [0x6c] = 7, 66 [0x0d] = 8, 67 [0x2d] = 10, 68 [0x4d] = 12, 69 [0x6d] = 14, 70 [0x0e] = 16, 71 [0x2e] = 20, 72 [0x4e] = 24, 73 [0x6e] = 28, 74 [0x0f] = 32, 75 [0x2f] = 40, 76 [0x4f] = 48, 77 [0x6f] = 56, 78 [0x10] = 64, 79 [0x30] = 80, 80 [0x50] = 96, 81 [0x70] = 112, 82 [0x11] = 128, 83 }; 84 85 int arch_cpu_init_dm(void) 86 { 87 struct udevice *dev; 88 int ret; 89 90 /* Start up the LPC so we have serial */ 91 ret = uclass_first_device(UCLASS_LPC, &dev); 92 if (ret) 93 return ret; 94 if (!dev) 95 return -ENODEV; 96 ret = cpu_set_flex_ratio_to_tdp_nominal(); 97 if (ret) 98 return ret; 99 100 return 0; 101 } 102 103 void set_max_freq(void) 104 { 105 msr_t msr, perf_ctl, platform_info; 106 107 /* Check for configurable TDP option */ 108 platform_info = msr_read(MSR_PLATFORM_INFO); 109 110 if ((platform_info.hi >> 1) & 3) { 111 /* Set to nominal TDP ratio */ 112 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 113 perf_ctl.lo = (msr.lo & 0xff) << 8; 114 } else { 115 /* Platform Info bits 15:8 give max ratio */ 116 msr = msr_read(MSR_PLATFORM_INFO); 117 perf_ctl.lo = msr.lo & 0xff00; 118 } 119 120 perf_ctl.hi = 0; 121 msr_write(IA32_PERF_CTL, perf_ctl); 122 123 debug("CPU: frequency set to %d MHz\n", 124 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); 125 } 126 127 int arch_cpu_init(void) 128 { 129 post_code(POST_CPU_INIT); 130 131 return x86_cpu_init_f(); 132 } 133 134 int checkcpu(void) 135 { 136 int ret; 137 138 set_max_freq(); 139 140 ret = cpu_common_init(); 141 if (ret) 142 return ret; 143 gd->arch.pei_boot_mode = PEI_BOOT_NONE; 144 145 return 0; 146 } 147 148 int print_cpuinfo(void) 149 { 150 char processor_name[CPU_MAX_NAME_LEN]; 151 const char *name; 152 153 /* Print processor name */ 154 name = cpu_get_name(processor_name); 155 printf("CPU: %s\n", name); 156 157 return 0; 158 } 159 160 /* 161 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate 162 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly 163 * when a core is woken up 164 */ 165 static int pcode_ready(void) 166 { 167 int wait_count; 168 const int delay_step = 10; 169 170 wait_count = 0; 171 do { 172 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 173 MAILBOX_RUN_BUSY)) 174 return 0; 175 wait_count += delay_step; 176 udelay(delay_step); 177 } while (wait_count < 1000); 178 179 return -ETIMEDOUT; 180 } 181 182 static u32 pcode_mailbox_read(u32 command) 183 { 184 int ret; 185 186 ret = pcode_ready(); 187 if (ret) { 188 debug("PCODE: mailbox timeout on wait ready\n"); 189 return ret; 190 } 191 192 /* Send command and start transaction */ 193 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); 194 195 ret = pcode_ready(); 196 if (ret) { 197 debug("PCODE: mailbox timeout on completion\n"); 198 return ret; 199 } 200 201 /* Read mailbox */ 202 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA)); 203 } 204 205 static int pcode_mailbox_write(u32 command, u32 data) 206 { 207 int ret; 208 209 ret = pcode_ready(); 210 if (ret) { 211 debug("PCODE: mailbox timeout on wait ready\n"); 212 return ret; 213 } 214 215 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA)); 216 217 /* Send command and start transaction */ 218 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); 219 220 ret = pcode_ready(); 221 if (ret) { 222 debug("PCODE: mailbox timeout on completion\n"); 223 return ret; 224 } 225 226 return 0; 227 } 228 229 /* @dev is the CPU device */ 230 static void initialize_vr_config(struct udevice *dev) 231 { 232 int ramp, min_vid; 233 msr_t msr; 234 235 debug("Initializing VR config\n"); 236 237 /* Configure VR_CURRENT_CONFIG */ 238 msr = msr_read(MSR_VR_CURRENT_CONFIG); 239 /* 240 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid 241 * on ULT systems 242 */ 243 msr.hi &= 0xc0000000; 244 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */ 245 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */ 246 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */ 247 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ 248 /* Leave the max instantaneous current limit (12:0) to default */ 249 msr_write(MSR_VR_CURRENT_CONFIG, msr); 250 251 /* Configure VR_MISC_CONFIG MSR */ 252 msr = msr_read(MSR_VR_MISC_CONFIG); 253 /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */ 254 msr.hi &= ~(0x3ff << (40 - 32)); 255 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ 256 /* Set IOUT_OFFSET to 0 */ 257 msr.hi &= ~0xff; 258 /* Set entry ramp rate to slow */ 259 msr.hi &= ~(1 << (51 - 32)); 260 /* Enable decay mode on C-state entry */ 261 msr.hi |= (1 << (52 - 32)); 262 /* Set the slow ramp rate */ 263 msr.hi &= ~(0x3 << (53 - 32)); 264 /* Configure the C-state exit ramp rate */ 265 ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 266 "intel,slow-ramp", -1); 267 if (ramp != -1) { 268 /* Configured slow ramp rate */ 269 msr.hi |= ((ramp & 0x3) << (53 - 32)); 270 /* Set exit ramp rate to slow */ 271 msr.hi &= ~(1 << (50 - 32)); 272 } else { 273 /* Fast ramp rate / 4 */ 274 msr.hi |= (0x01 << (53 - 32)); 275 /* Set exit ramp rate to fast */ 276 msr.hi |= (1 << (50 - 32)); 277 } 278 /* Set MIN_VID (31:24) to allow CPU to have full control */ 279 msr.lo &= ~0xff000000; 280 min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 281 "intel,min-vid", 0); 282 msr.lo |= (min_vid & 0xff) << 24; 283 msr_write(MSR_VR_MISC_CONFIG, msr); 284 285 /* Configure VR_MISC_CONFIG2 MSR */ 286 msr = msr_read(MSR_VR_MISC_CONFIG2); 287 msr.lo &= ~0xffff; 288 /* 289 * Allow CPU to control minimum voltage completely (15:8) and 290 * set the fast ramp voltage in 10mV steps 291 */ 292 if (cpu_get_family_model() == BROADWELL_FAMILY_ULT) 293 msr.lo |= 0x006a; /* 1.56V */ 294 else 295 msr.lo |= 0x006f; /* 1.60V */ 296 msr_write(MSR_VR_MISC_CONFIG2, msr); 297 298 /* Set C9/C10 VCC Min */ 299 pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); 300 } 301 302 static int calibrate_24mhz_bclk(void) 303 { 304 int err_code; 305 int ret; 306 307 ret = pcode_ready(); 308 if (ret) 309 return ret; 310 311 /* A non-zero value initiates the PCODE calibration */ 312 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA)); 313 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL, 314 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); 315 316 ret = pcode_ready(); 317 if (ret) 318 return ret; 319 320 err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff; 321 322 debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code); 323 324 /* Read the calibrated value */ 325 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION, 326 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); 327 328 ret = pcode_ready(); 329 if (ret) 330 return ret; 331 332 debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n", 333 readl(MCHBAR_REG(BIOS_MAILBOX_DATA))); 334 335 return 0; 336 } 337 338 static void configure_pch_power_sharing(void) 339 { 340 u32 pch_power, pch_power_ext, pmsync, pmsync2; 341 int i; 342 343 /* Read PCH Power levels from PCODE */ 344 pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); 345 pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); 346 347 debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power, 348 pch_power_ext); 349 350 pmsync = readl(RCB_REG(PMSYNC_CONFIG)); 351 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2)); 352 353 /* 354 * Program PMSYNC_TPR_CONFIG PCH power limit values 355 * pmsync[0:4] = mailbox[0:5] 356 * pmsync[8:12] = mailbox[6:11] 357 * pmsync[16:20] = mailbox[12:17] 358 */ 359 for (i = 0; i < 3; i++) { 360 u32 level = pch_power & 0x3f; 361 pch_power >>= 6; 362 pmsync &= ~(0x1f << (i * 8)); 363 pmsync |= (level & 0x1f) << (i * 8); 364 } 365 writel(pmsync, RCB_REG(PMSYNC_CONFIG)); 366 367 /* 368 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values 369 * pmsync2[0:4] = mailbox[23:18] 370 * pmsync2[8:12] = mailbox_ext[6:11] 371 * pmsync2[16:20] = mailbox_ext[12:17] 372 * pmsync2[24:28] = mailbox_ext[18:22] 373 */ 374 pmsync2 &= ~0x1f; 375 pmsync2 |= pch_power & 0x1f; 376 377 for (i = 1; i < 4; i++) { 378 u32 level = pch_power_ext & 0x3f; 379 pch_power_ext >>= 6; 380 pmsync2 &= ~(0x1f << (i * 8)); 381 pmsync2 |= (level & 0x1f) << (i * 8); 382 } 383 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2)); 384 } 385 386 static int bsp_init_before_ap_bringup(struct udevice *dev) 387 { 388 int ret; 389 390 initialize_vr_config(dev); 391 ret = calibrate_24mhz_bclk(); 392 if (ret) 393 return ret; 394 configure_pch_power_sharing(); 395 396 return 0; 397 } 398 399 int cpu_config_tdp_levels(void) 400 { 401 msr_t platform_info; 402 403 /* Bits 34:33 indicate how many levels supported */ 404 platform_info = msr_read(MSR_PLATFORM_INFO); 405 return (platform_info.hi >> 1) & 3; 406 } 407 408 static void set_max_ratio(void) 409 { 410 msr_t msr, perf_ctl; 411 412 perf_ctl.hi = 0; 413 414 /* Check for configurable TDP option */ 415 if (turbo_get_state() == TURBO_ENABLED) { 416 msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT); 417 perf_ctl.lo = (msr.lo & 0xff) << 8; 418 } else if (cpu_config_tdp_levels()) { 419 /* Set to nominal TDP ratio */ 420 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 421 perf_ctl.lo = (msr.lo & 0xff) << 8; 422 } else { 423 /* Platform Info bits 15:8 give max ratio */ 424 msr = msr_read(MSR_PLATFORM_INFO); 425 perf_ctl.lo = msr.lo & 0xff00; 426 } 427 msr_write(IA32_PERF_CTL, perf_ctl); 428 429 debug("cpu: frequency set to %d\n", 430 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); 431 } 432 433 int broadwell_init(struct udevice *dev) 434 { 435 struct cpu_broadwell_priv *priv = dev_get_priv(dev); 436 int num_threads; 437 int num_cores; 438 msr_t msr; 439 int ret; 440 441 msr = msr_read(CORE_THREAD_COUNT_MSR); 442 num_threads = (msr.lo >> 0) & 0xffff; 443 num_cores = (msr.lo >> 16) & 0xffff; 444 debug("CPU has %u cores, %u threads enabled\n", num_cores, 445 num_threads); 446 447 priv->ht_disabled = num_threads == num_cores; 448 449 ret = bsp_init_before_ap_bringup(dev); 450 if (ret) 451 return ret; 452 453 set_max_ratio(); 454 455 return ret; 456 } 457 458 static void configure_mca(void) 459 { 460 msr_t msr; 461 const unsigned int mcg_cap_msr = 0x179; 462 int i; 463 int num_banks; 464 465 msr = msr_read(mcg_cap_msr); 466 num_banks = msr.lo & 0xff; 467 msr.lo = 0; 468 msr.hi = 0; 469 /* 470 * TODO(adurbin): This should only be done on a cold boot. Also, some 471 * of these banks are core vs package scope. For now every CPU clears 472 * every bank 473 */ 474 for (i = 0; i < num_banks; i++) 475 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr); 476 } 477 478 static void enable_lapic_tpr(void) 479 { 480 msr_t msr; 481 482 msr = msr_read(MSR_PIC_MSG_CONTROL); 483 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ 484 msr_write(MSR_PIC_MSG_CONTROL, msr); 485 } 486 487 488 static void configure_c_states(void) 489 { 490 msr_t msr; 491 492 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL); 493 msr.lo |= (1 << 31); /* Timed MWAIT Enable */ 494 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */ 495 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */ 496 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ 497 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ 498 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ 499 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ 500 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ 501 /* The deepest package c-state defaults to factory-configured value */ 502 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr); 503 504 msr = msr_read(MSR_MISC_PWR_MGMT); 505 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ 506 msr_write(MSR_MISC_PWR_MGMT, msr); 507 508 msr = msr_read(MSR_POWER_CTL); 509 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ 510 msr.lo |= (1 << 1); /* C1E Enable */ 511 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ 512 msr_write(MSR_POWER_CTL, msr); 513 514 /* C-state Interrupt Response Latency Control 0 - package C3 latency */ 515 msr.hi = 0; 516 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; 517 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr); 518 519 /* C-state Interrupt Response Latency Control 1 */ 520 msr.hi = 0; 521 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; 522 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr); 523 524 /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ 525 msr.hi = 0; 526 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; 527 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr); 528 529 /* C-state Interrupt Response Latency Control 3 - package C8 */ 530 msr.hi = 0; 531 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; 532 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr); 533 534 /* C-state Interrupt Response Latency Control 4 - package C9 */ 535 msr.hi = 0; 536 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; 537 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr); 538 539 /* C-state Interrupt Response Latency Control 5 - package C10 */ 540 msr.hi = 0; 541 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; 542 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr); 543 } 544 545 static void configure_misc(void) 546 { 547 msr_t msr; 548 549 msr = msr_read(MSR_IA32_MISC_ENABLE); 550 msr.lo |= (1 << 0); /* Fast String enable */ 551 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ 552 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ 553 msr_write(MSR_IA32_MISC_ENABLE, msr); 554 555 /* Disable thermal interrupts */ 556 msr.lo = 0; 557 msr.hi = 0; 558 msr_write(MSR_IA32_THERM_INTERRUPT, msr); 559 560 /* Enable package critical interrupt only */ 561 msr.lo = 1 << 4; 562 msr.hi = 0; 563 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr); 564 } 565 566 static void configure_thermal_target(struct udevice *dev) 567 { 568 int tcc_offset; 569 msr_t msr; 570 571 tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 572 "intel,tcc-offset", 0); 573 574 /* Set TCC activaiton offset if supported */ 575 msr = msr_read(MSR_PLATFORM_INFO); 576 if ((msr.lo & (1 << 30)) && tcc_offset) { 577 msr = msr_read(MSR_TEMPERATURE_TARGET); 578 msr.lo &= ~(0xf << 24); /* Bits 27:24 */ 579 msr.lo |= (tcc_offset & 0xf) << 24; 580 msr_write(MSR_TEMPERATURE_TARGET, msr); 581 } 582 } 583 584 static void configure_dca_cap(void) 585 { 586 struct cpuid_result cpuid_regs; 587 msr_t msr; 588 589 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ 590 cpuid_regs = cpuid(1); 591 if (cpuid_regs.ecx & (1 << 18)) { 592 msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP); 593 msr.lo |= 1; 594 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr); 595 } 596 } 597 598 static void set_energy_perf_bias(u8 policy) 599 { 600 msr_t msr; 601 int ecx; 602 603 /* Determine if energy efficient policy is supported */ 604 ecx = cpuid_ecx(0x6); 605 if (!(ecx & (1 << 3))) 606 return; 607 608 /* Energy Policy is bits 3:0 */ 609 msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS); 610 msr.lo &= ~0xf; 611 msr.lo |= policy & 0xf; 612 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr); 613 614 debug("cpu: energy policy set to %u\n", policy); 615 } 616 617 /* All CPUs including BSP will run the following function */ 618 static void cpu_core_init(struct udevice *dev) 619 { 620 /* Clear out pending MCEs */ 621 configure_mca(); 622 623 /* Enable the local cpu apics */ 624 enable_lapic_tpr(); 625 626 /* Configure C States */ 627 configure_c_states(); 628 629 /* Configure Enhanced SpeedStep and Thermal Sensors */ 630 configure_misc(); 631 632 /* Thermal throttle activation offset */ 633 configure_thermal_target(dev); 634 635 /* Enable Direct Cache Access */ 636 configure_dca_cap(); 637 638 /* Set energy policy */ 639 set_energy_perf_bias(ENERGY_POLICY_NORMAL); 640 641 /* Enable Turbo */ 642 turbo_enable(); 643 } 644 645 /* 646 * Configure processor power limits if possible 647 * This must be done AFTER set of BIOS_RESET_CPL 648 */ 649 void cpu_set_power_limits(int power_limit_1_time) 650 { 651 msr_t msr; 652 msr_t limit; 653 unsigned power_unit; 654 unsigned tdp, min_power, max_power, max_time; 655 u8 power_limit_1_val; 656 657 msr = msr_read(MSR_PLATFORM_INFO); 658 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) 659 power_limit_1_time = 28; 660 661 if (!(msr.lo & PLATFORM_INFO_SET_TDP)) 662 return; 663 664 /* Get units */ 665 msr = msr_read(MSR_PKG_POWER_SKU_UNIT); 666 power_unit = 2 << ((msr.lo & 0xf) - 1); 667 668 /* Get power defaults for this SKU */ 669 msr = msr_read(MSR_PKG_POWER_SKU); 670 tdp = msr.lo & 0x7fff; 671 min_power = (msr.lo >> 16) & 0x7fff; 672 max_power = msr.hi & 0x7fff; 673 max_time = (msr.hi >> 16) & 0x7f; 674 675 debug("CPU TDP: %u Watts\n", tdp / power_unit); 676 677 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) 678 power_limit_1_time = power_limit_time_msr_to_sec[max_time]; 679 680 if (min_power > 0 && tdp < min_power) 681 tdp = min_power; 682 683 if (max_power > 0 && tdp > max_power) 684 tdp = max_power; 685 686 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; 687 688 /* Set long term power limit to TDP */ 689 limit.lo = 0; 690 limit.lo |= tdp & PKG_POWER_LIMIT_MASK; 691 limit.lo |= PKG_POWER_LIMIT_EN; 692 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << 693 PKG_POWER_LIMIT_TIME_SHIFT; 694 695 /* Set short term power limit to 1.25 * TDP */ 696 limit.hi = 0; 697 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; 698 limit.hi |= PKG_POWER_LIMIT_EN; 699 /* Power limit 2 time is only programmable on server SKU */ 700 701 msr_write(MSR_PKG_POWER_LIMIT, limit); 702 703 /* Set power limit values in MCHBAR as well */ 704 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO)); 705 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI)); 706 707 /* Set DDR RAPL power limit by copying from MMIO to MSR */ 708 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO)); 709 msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI)); 710 msr_write(MSR_DDR_RAPL_LIMIT, msr); 711 712 /* Use nominal TDP values for CPUs with configurable TDP */ 713 if (cpu_config_tdp_levels()) { 714 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); 715 limit.hi = 0; 716 limit.lo = msr.lo & 0xff; 717 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit); 718 } 719 } 720 721 static int broadwell_get_info(struct udevice *dev, struct cpu_info *info) 722 { 723 msr_t msr; 724 725 msr = msr_read(IA32_PERF_CTL); 726 info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000; 727 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | 728 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID; 729 730 return 0; 731 } 732 733 static int broadwell_get_count(struct udevice *dev) 734 { 735 return 4; 736 } 737 738 static int cpu_x86_broadwell_probe(struct udevice *dev) 739 { 740 if (dev->seq == 0) { 741 cpu_core_init(dev); 742 return broadwell_init(dev); 743 } 744 745 return 0; 746 } 747 748 static const struct cpu_ops cpu_x86_broadwell_ops = { 749 .get_desc = cpu_x86_get_desc, 750 .get_info = broadwell_get_info, 751 .get_count = broadwell_get_count, 752 .get_vendor = cpu_x86_get_vendor, 753 }; 754 755 static const struct udevice_id cpu_x86_broadwell_ids[] = { 756 { .compatible = "intel,core-i3-gen5" }, 757 { } 758 }; 759 760 U_BOOT_DRIVER(cpu_x86_broadwell_drv) = { 761 .name = "cpu_x86_broadwell", 762 .id = UCLASS_CPU, 763 .of_match = cpu_x86_broadwell_ids, 764 .bind = cpu_x86_bind, 765 .probe = cpu_x86_broadwell_probe, 766 .ops = &cpu_x86_broadwell_ops, 767 .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv), 768 }; 769