1*23e8bd7eSSimon Glass // SPDX-License-Identifier: GPL-2.0
2*23e8bd7eSSimon Glass /*
3*23e8bd7eSSimon Glass * Support for Intel Application Digital Signal Processor
4*23e8bd7eSSimon Glass *
5*23e8bd7eSSimon Glass * Copyright 2019 Google LLC
6*23e8bd7eSSimon Glass *
7*23e8bd7eSSimon Glass * Modified from coreboot file of the same name
8*23e8bd7eSSimon Glass */
9*23e8bd7eSSimon Glass
10*23e8bd7eSSimon Glass #define LOG_CATEGORY UCLASS_SYSCON
11*23e8bd7eSSimon Glass
12*23e8bd7eSSimon Glass #include <common.h>
13*23e8bd7eSSimon Glass #include <dm.h>
14*23e8bd7eSSimon Glass #include <pci.h>
15*23e8bd7eSSimon Glass #include <asm/io.h>
16*23e8bd7eSSimon Glass #include <asm/cpu.h>
17*23e8bd7eSSimon Glass #include <asm/intel_regs.h>
18*23e8bd7eSSimon Glass #include <asm/arch/adsp.h>
19*23e8bd7eSSimon Glass #include <asm/arch/pch.h>
20*23e8bd7eSSimon Glass #include <asm/arch/rcb.h>
21*23e8bd7eSSimon Glass
22*23e8bd7eSSimon Glass enum pci_type_t {
23*23e8bd7eSSimon Glass LYNX_POINT,
24*23e8bd7eSSimon Glass WILDCAT_POINT,
25*23e8bd7eSSimon Glass };
26*23e8bd7eSSimon Glass
27*23e8bd7eSSimon Glass struct broadwell_adsp_priv {
28*23e8bd7eSSimon Glass bool adsp_d3_pg_enable;
29*23e8bd7eSSimon Glass bool adsp_sram_pg_enable;
30*23e8bd7eSSimon Glass bool sio_acpi_mode;
31*23e8bd7eSSimon Glass };
32*23e8bd7eSSimon Glass
broadwell_adsp_probe(struct udevice * dev)33*23e8bd7eSSimon Glass static int broadwell_adsp_probe(struct udevice *dev)
34*23e8bd7eSSimon Glass {
35*23e8bd7eSSimon Glass struct broadwell_adsp_priv *priv = dev_get_priv(dev);
36*23e8bd7eSSimon Glass enum pci_type_t type;
37*23e8bd7eSSimon Glass u32 bar0, bar1;
38*23e8bd7eSSimon Glass u32 tmp32;
39*23e8bd7eSSimon Glass
40*23e8bd7eSSimon Glass /* Find BAR0 and BAR1 */
41*23e8bd7eSSimon Glass bar0 = dm_pci_read_bar32(dev, 0);
42*23e8bd7eSSimon Glass if (!bar0)
43*23e8bd7eSSimon Glass return -EINVAL;
44*23e8bd7eSSimon Glass bar1 = dm_pci_read_bar32(dev, 1);
45*23e8bd7eSSimon Glass if (!bar1)
46*23e8bd7eSSimon Glass return -EINVAL;
47*23e8bd7eSSimon Glass
48*23e8bd7eSSimon Glass /*
49*23e8bd7eSSimon Glass * Set LTR value in DSP shim LTR control register to 3ms
50*23e8bd7eSSimon Glass * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
51*23e8bd7eSSimon Glass */
52*23e8bd7eSSimon Glass type = dev_get_driver_data(dev);
53*23e8bd7eSSimon Glass tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
54*23e8bd7eSSimon Glass writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32);
55*23e8bd7eSSimon Glass
56*23e8bd7eSSimon Glass /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
57*23e8bd7eSSimon Glass dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
58*23e8bd7eSSimon Glass
59*23e8bd7eSSimon Glass /* Program ADSP IOBP VDLDAT1 to 0x040100 */
60*23e8bd7eSSimon Glass pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
61*23e8bd7eSSimon Glass
62*23e8bd7eSSimon Glass /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
63*23e8bd7eSSimon Glass dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32);
64*23e8bd7eSSimon Glass if (type == WILDCAT_POINT) {
65*23e8bd7eSSimon Glass if (priv->adsp_d3_pg_enable) {
66*23e8bd7eSSimon Glass tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
67*23e8bd7eSSimon Glass if (priv->adsp_sram_pg_enable)
68*23e8bd7eSSimon Glass tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
69*23e8bd7eSSimon Glass else
70*23e8bd7eSSimon Glass tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
71*23e8bd7eSSimon Glass } else {
72*23e8bd7eSSimon Glass tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
73*23e8bd7eSSimon Glass }
74*23e8bd7eSSimon Glass } else {
75*23e8bd7eSSimon Glass if (priv->adsp_d3_pg_enable) {
76*23e8bd7eSSimon Glass tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
77*23e8bd7eSSimon Glass if (priv->adsp_sram_pg_enable)
78*23e8bd7eSSimon Glass tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
79*23e8bd7eSSimon Glass else
80*23e8bd7eSSimon Glass tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
81*23e8bd7eSSimon Glass } else {
82*23e8bd7eSSimon Glass tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
83*23e8bd7eSSimon Glass }
84*23e8bd7eSSimon Glass }
85*23e8bd7eSSimon Glass dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
86*23e8bd7eSSimon Glass
87*23e8bd7eSSimon Glass /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
88*23e8bd7eSSimon Glass setbits_le32(RCB_REG(0x3350), 1 << 10);
89*23e8bd7eSSimon Glass
90*23e8bd7eSSimon Glass /* Set DSP IOBP PMCTL 0x1e0=0x3f */
91*23e8bd7eSSimon Glass pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
92*23e8bd7eSSimon Glass
93*23e8bd7eSSimon Glass if (priv->sio_acpi_mode) {
94*23e8bd7eSSimon Glass /* Configure for ACPI mode */
95*23e8bd7eSSimon Glass log_info("ADSP: Enable ACPI Mode IRQ3\n");
96*23e8bd7eSSimon Glass
97*23e8bd7eSSimon Glass /* Set interrupt de-assert/assert opcode override to IRQ3 */
98*23e8bd7eSSimon Glass pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
99*23e8bd7eSSimon Glass
100*23e8bd7eSSimon Glass /* Enable IRQ3 in RCBA */
101*23e8bd7eSSimon Glass setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
102*23e8bd7eSSimon Glass
103*23e8bd7eSSimon Glass /* Set ACPI Interrupt Enable Bit */
104*23e8bd7eSSimon Glass pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
105*23e8bd7eSSimon Glass ADSP_PCICFGCTL_ACPIIE);
106*23e8bd7eSSimon Glass
107*23e8bd7eSSimon Glass /* Put ADSP in D3hot */
108*23e8bd7eSSimon Glass clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
109*23e8bd7eSSimon Glass } else {
110*23e8bd7eSSimon Glass log_info("ADSP: Enable PCI Mode IRQ23\n");
111*23e8bd7eSSimon Glass
112*23e8bd7eSSimon Glass /* Configure for PCI mode */
113*23e8bd7eSSimon Glass dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
114*23e8bd7eSSimon Glass
115*23e8bd7eSSimon Glass /* Clear ACPI Interrupt Enable Bit */
116*23e8bd7eSSimon Glass pch_iobp_update(ADSP_IOBP_PCICFGCTL,
117*23e8bd7eSSimon Glass ~(ADSP_PCICFGCTL_SPCBAD |
118*23e8bd7eSSimon Glass ADSP_PCICFGCTL_ACPIIE), 0);
119*23e8bd7eSSimon Glass }
120*23e8bd7eSSimon Glass
121*23e8bd7eSSimon Glass return 0;
122*23e8bd7eSSimon Glass }
123*23e8bd7eSSimon Glass
broadwell_adsp_ofdata_to_platdata(struct udevice * dev)124*23e8bd7eSSimon Glass static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev)
125*23e8bd7eSSimon Glass {
126*23e8bd7eSSimon Glass struct broadwell_adsp_priv *priv = dev_get_priv(dev);
127*23e8bd7eSSimon Glass
128*23e8bd7eSSimon Glass priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable");
129*23e8bd7eSSimon Glass priv->adsp_sram_pg_enable = dev_read_bool(dev,
130*23e8bd7eSSimon Glass "intel,adsp-sram-pg-enable");
131*23e8bd7eSSimon Glass priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode");
132*23e8bd7eSSimon Glass
133*23e8bd7eSSimon Glass return 0;
134*23e8bd7eSSimon Glass }
135*23e8bd7eSSimon Glass
136*23e8bd7eSSimon Glass static const struct udevice_id broadwell_adsp_ids[] = {
137*23e8bd7eSSimon Glass { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT },
138*23e8bd7eSSimon Glass { }
139*23e8bd7eSSimon Glass };
140*23e8bd7eSSimon Glass
141*23e8bd7eSSimon Glass U_BOOT_DRIVER(broadwell_adsp_drv) = {
142*23e8bd7eSSimon Glass .name = "adsp",
143*23e8bd7eSSimon Glass .id = UCLASS_SYSCON,
144*23e8bd7eSSimon Glass .ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata,
145*23e8bd7eSSimon Glass .of_match = broadwell_adsp_ids,
146*23e8bd7eSSimon Glass .bind = dm_scan_fdt_dev,
147*23e8bd7eSSimon Glass .probe = broadwell_adsp_probe,
148*23e8bd7eSSimon Glass };
149*23e8bd7eSSimon Glass
150*23e8bd7eSSimon Glass static struct pci_device_id broadwell_adsp_supported[] = {
151*23e8bd7eSSimon Glass { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
152*23e8bd7eSSimon Glass PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) },
153*23e8bd7eSSimon Glass { },
154*23e8bd7eSSimon Glass };
155*23e8bd7eSSimon Glass
156*23e8bd7eSSimon Glass U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported);
157