1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4  */
5 
6 #include <common.h>
7 #include <mmc.h>
8 #include <pci_ids.h>
9 #include <asm/irq.h>
10 #include <asm/mrccache.h>
11 #include <asm/post.h>
12 #include <asm/arch/iomap.h>
13 
14 /* GPIO SUS */
15 #define GPIO_SUS_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
16 #define GPIO_SUS_DFX5_CONF0	0x150
17 #define BYT_TRIG_LVL		BIT(24)
18 #define BYT_TRIG_POS		BIT(25)
19 
20 int arch_cpu_init(void)
21 {
22 	post_code(POST_CPU_INIT);
23 
24 	return x86_cpu_init_f();
25 }
26 
27 int arch_misc_init(void)
28 {
29 	if (!ll_boot_init())
30 		return 0;
31 
32 #ifdef CONFIG_ENABLE_MRC_CACHE
33 	/*
34 	 * We intend not to check any return value here, as even MRC cache
35 	 * is not saved successfully, it is not a severe error that will
36 	 * prevent system from continuing to boot.
37 	 */
38 	mrccache_save();
39 #endif
40 
41 	/*
42 	 * For some unknown reason, FSP (gold4) for BayTrail configures
43 	 * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
44 	 * This does not cause any issue when Linux kernel runs w/ or w/o
45 	 * the pinctrl driver for BayTrail. However this causes unstable
46 	 * S3 resume if the pinctrl driver is included in the kernel build.
47 	 * As this pin keeps generating interrupts during an S3 resume,
48 	 * and there is no IRQ requester in the kernel to handle it, the
49 	 * kernel seems to hang and does not continue resuming.
50 	 *
51 	 * Clear the mysterious interrupt bits for this pin.
52 	 */
53 	clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
54 		     BYT_TRIG_LVL | BYT_TRIG_POS);
55 
56 	return 0;
57 }
58 
59 void reset_cpu(ulong addr)
60 {
61 	/* cold reset */
62 	x86_full_reset();
63 }
64