1 /*
2  * Copyright (C) 2013, Intel Corporation
3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4  *
5  * SPDX-License-Identifier:	Intel
6  */
7 
8 #include <common.h>
9 #include <asm/arch/fsp/azalia.h>
10 #include <asm/fsp/fsp_support.h>
11 
12 /* ALC262 Verb Table - 10EC0262 */
13 static const uint32_t verb_table_data13[] = {
14 	/* Pin Complex (NID 0x11) */
15 	0x01171cf0,
16 	0x01171d11,
17 	0x01171e11,
18 	0x01171f41,
19 	/* Pin Complex (NID 0x12) */
20 	0x01271cf0,
21 	0x01271d11,
22 	0x01271e11,
23 	0x01271f41,
24 	/* Pin Complex (NID 0x14) */
25 	0x01471c10,
26 	0x01471d40,
27 	0x01471e01,
28 	0x01471f01,
29 	/* Pin Complex (NID 0x15) */
30 	0x01571cf0,
31 	0x01571d11,
32 	0x01571e11,
33 	0x01571f41,
34 	/* Pin Complex (NID 0x16) */
35 	0x01671cf0,
36 	0x01671d11,
37 	0x01671e11,
38 	0x01671f41,
39 	/* Pin Complex (NID 0x18) */
40 	0x01871c20,
41 	0x01871d98,
42 	0x01871ea1,
43 	0x01871f01,
44 	/* Pin Complex (NID 0x19) */
45 	0x01971c21,
46 	0x01971d98,
47 	0x01971ea1,
48 	0x01971f02,
49 	/* Pin Complex (NID 0x1A) */
50 	0x01a71c2f,
51 	0x01a71d30,
52 	0x01a71e81,
53 	0x01a71f01,
54 	/* Pin Complex */
55 	0x01b71c1f,
56 	0x01b71d40,
57 	0x01b71e21,
58 	0x01b71f02,
59 	/* Pin Complex */
60 	0x01c71cf0,
61 	0x01c71d11,
62 	0x01c71e11,
63 	0x01c71f41,
64 	/* Pin Complex */
65 	0x01d71c01,
66 	0x01d71dc6,
67 	0x01d71e14,
68 	0x01d71f40,
69 	/* Pin Complex */
70 	0x01e71cf0,
71 	0x01e71d11,
72 	0x01e71e11,
73 	0x01e71f41,
74 	/* Pin Complex */
75 	0x01f71cf0,
76 	0x01f71d11,
77 	0x01f71e11,
78 	0x01f71f41,
79 };
80 
81 /*
82  * This needs to be in ROM since if we put it in CAR, FSP init loses it when
83  * it drops CAR.
84  *
85  * TODO(sjg@chromium.org): Move to device tree when FSP allows it
86  *
87  * VerbTable: (RealTek ALC262)
88  * Revision ID = 0xFF, support all steps
89  * Codec Verb Table For AZALIA
90  * Codec Address: CAd value (0/1/2)
91  * Codec Vendor: 0x10EC0262
92  */
93 static const struct pch_azalia_verb_table azalia_verb_table[] = {
94 	{
95 		{
96 			0x10ec0262,
97 			0x0000,
98 			0xff,
99 			0x01,
100 			0x000b,
101 			0x0002,
102 		},
103 		verb_table_data13
104 	}
105 };
106 
107 const struct pch_azalia_config azalia_config = {
108 	.pme_enable = 1,
109 	.docking_supported = 1,
110 	.docking_attached = 0,
111 	.hdmi_codec_enable = 1,
112 	.azalia_v_ci_enable = 1,
113 	.rsvdbits = 0,
114 	.azalia_verb_table_num = 1,
115 	.azalia_verb_table = azalia_verb_table,
116 	.reset_wait_timer_us = 300
117 };
118 
119 void update_fsp_upd(struct upd_region *fsp_upd)
120 {
121 	struct memory_down_data *mem;
122 
123 	/*
124 	 * Configure everything here to avoid the poor hard-pressed user
125 	 * needing to run Intel's binary configuration tool. It may also allow
126 	 * us to support the 1GB single core variant easily.
127 	 *
128 	 * TODO(sjg@chromium.org): Move to device tree
129 	 */
130 	fsp_upd->mrc_init_tseg_size = 8;
131 	fsp_upd->mrc_init_mmio_size = 0x800;
132 	fsp_upd->emmc_boot_mode = 0xff;
133 	fsp_upd->enable_sdio = 1;
134 	fsp_upd->enable_sdcard = 1;
135 	fsp_upd->enable_hsuart0 = 1;
136 	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
137 	fsp_upd->enable_i2_c0 = 0;
138 	fsp_upd->enable_i2_c2 = 0;
139 	fsp_upd->enable_i2_c3 = 0;
140 	fsp_upd->enable_i2_c4 = 0;
141 	fsp_upd->enable_xhci = 0;
142 	fsp_upd->igd_render_standby = 1;
143 
144 	mem = &fsp_upd->memory_params;
145 	mem->enable_memory_down = 1;
146 	mem->dram_speed = 1;
147 	mem->dimm_width = 1;
148 	mem->dimm_density = 2;
149 	mem->dimm_tcl = 0xb;
150 	mem->dimm_trpt_rcd = 0xb;
151 	mem->dimm_twr = 0xc;
152 	mem->dimm_twtr = 6;
153 	mem->dimm_trrd = 6;
154 	mem->dimm_trtp = 6;
155 	mem->dimm_tfaw = 0x14;
156 }
157