xref: /openbmc/u-boot/arch/x86/cpu/baytrail/fsp_configs.c (revision abddcd52ab4979a57dc90ce1b90f8121b43d91b2)
1 /*
2  * Copyright (C) 2013, Intel Corporation
3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4  * Copyright (C) 2015, Kodak Alaris, Inc
5  *
6  * SPDX-License-Identifier:	Intel
7  */
8 
9 #include <common.h>
10 #include <fdtdec.h>
11 #include <asm/fsp/fsp_support.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 /* ALC262 Verb Table - 10EC0262 */
16 static const u32 verb_table_data13[] = {
17 	/* Pin Complex (NID 0x11) */
18 	0x01171cf0,
19 	0x01171d11,
20 	0x01171e11,
21 	0x01171f41,
22 	/* Pin Complex (NID 0x12) */
23 	0x01271cf0,
24 	0x01271d11,
25 	0x01271e11,
26 	0x01271f41,
27 	/* Pin Complex (NID 0x14) */
28 	0x01471c10,
29 	0x01471d40,
30 	0x01471e01,
31 	0x01471f01,
32 	/* Pin Complex (NID 0x15) */
33 	0x01571cf0,
34 	0x01571d11,
35 	0x01571e11,
36 	0x01571f41,
37 	/* Pin Complex (NID 0x16) */
38 	0x01671cf0,
39 	0x01671d11,
40 	0x01671e11,
41 	0x01671f41,
42 	/* Pin Complex (NID 0x18) */
43 	0x01871c20,
44 	0x01871d98,
45 	0x01871ea1,
46 	0x01871f01,
47 	/* Pin Complex (NID 0x19) */
48 	0x01971c21,
49 	0x01971d98,
50 	0x01971ea1,
51 	0x01971f02,
52 	/* Pin Complex (NID 0x1A) */
53 	0x01a71c2f,
54 	0x01a71d30,
55 	0x01a71e81,
56 	0x01a71f01,
57 	/* Pin Complex */
58 	0x01b71c1f,
59 	0x01b71d40,
60 	0x01b71e21,
61 	0x01b71f02,
62 	/* Pin Complex */
63 	0x01c71cf0,
64 	0x01c71d11,
65 	0x01c71e11,
66 	0x01c71f41,
67 	/* Pin Complex */
68 	0x01d71c01,
69 	0x01d71dc6,
70 	0x01d71e14,
71 	0x01d71f40,
72 	/* Pin Complex */
73 	0x01e71cf0,
74 	0x01e71d11,
75 	0x01e71e11,
76 	0x01e71f41,
77 	/* Pin Complex */
78 	0x01f71cf0,
79 	0x01f71d11,
80 	0x01f71e11,
81 	0x01f71f41,
82 };
83 
84 /*
85  * This needs to be in ROM since if we put it in CAR, FSP init loses it when
86  * it drops CAR.
87  *
88  * TODO(sjg@chromium.org): Move to device tree when FSP allows it
89  *
90  * VerbTable: (RealTek ALC262)
91  * Revision ID = 0xFF, support all steps
92  * Codec Verb Table For AZALIA
93  * Codec Address: CAd value (0/1/2)
94  * Codec Vendor: 0x10EC0262
95  */
96 static const struct azalia_verb_table azalia_verb_table[] = {
97 	{
98 		{
99 			0x10ec0262,
100 			0x0000,
101 			0xff,
102 			0x01,
103 			0x000b,
104 			0x0002,
105 		},
106 		verb_table_data13
107 	}
108 };
109 
110 const struct azalia_config azalia_config = {
111 	.pme_enable = 1,
112 	.docking_supported = 1,
113 	.docking_attached = 0,
114 	.hdmi_codec_enable = 1,
115 	.azalia_v_ci_enable = 1,
116 	.rsvdbits = 0,
117 	.verb_table_num = 1,
118 	.verb_table = azalia_verb_table,
119 	.reset_wait_timer_ms = 300
120 };
121 
122 /**
123  * Override the FSP's configuration data.
124  * If the device tree does not specify an integer setting, use the default
125  * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
126  */
127 void update_fsp_configs(struct fsp_config_data *config,
128 			struct fspinit_rtbuf *rt_buf)
129 {
130 	struct upd_region *fsp_upd = &config->fsp_upd;
131 	struct memory_down_data *mem;
132 	const void *blob = gd->fdt_blob;
133 	int node;
134 
135 	/* Initialize runtime buffer for fsp_init() */
136 	rt_buf->common.stack_top = config->common.stack_top - 32;
137 	rt_buf->common.boot_mode = config->common.boot_mode;
138 	rt_buf->common.upd_data = &config->fsp_upd;
139 
140 	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
141 
142 	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
143 	if (node < 0) {
144 		debug("%s: Cannot find FSP node\n", __func__);
145 		return;
146 	}
147 
148 	fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
149 						     "fsp,mrc-init-tseg-size",
150 						     MRC_INIT_TSEG_SIZE_1MB);
151 	fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
152 						     "fsp,mrc-init-mmio-size",
153 						     MRC_INIT_MMIO_SIZE_2048MB);
154 	fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
155 						     "fsp,mrc-init-spd-addr1",
156 						     0xa0);
157 	fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
158 						     "fsp,mrc-init-spd-addr2",
159 						     0xa2);
160 	fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node,
161 						 "fsp,emmc-boot-mode",
162 						 EMMC_BOOT_MODE_EMMC41);
163 	fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio");
164 	fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node,
165 						 "fsp,enable-sdcard");
166 	fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
167 						  "fsp,enable-hsuart0");
168 	fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
169 						  "fsp,enable-hsuart1");
170 	fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi");
171 	fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata");
172 	fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode",
173 					    SATA_MODE_AHCI);
174 	fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
175 						 "fsp,enable-azalia");
176 	fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
177 	fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
178 					   LPE_MODE_PCI);
179 	fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode",
180 					   LPSS_SIO_MODE_PCI);
181 	fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
182 	fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
183 	fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
184 	fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1");
185 	fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2");
186 	fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3");
187 	fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4");
188 	fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5");
189 	fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6");
190 	fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0");
191 	fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1");
192 	fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi");
193 	fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
194 			"fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB);
195 	fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
196 						APERTURE_SIZE_256MB);
197 	fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size",
198 					   GTT_SIZE_2MB);
199 	fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
200 						 "fsp,mrc-debug-msg");
201 	fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
202 	fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode",
203 					   SCC_MODE_PCI);
204 	fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
205 						      "fsp,igd-render-standby");
206 	fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
207 						  "fsp,txe-uma-enable");
208 	fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection",
209 					       OS_SELECTION_LINUX);
210 	fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node,
211 			"fsp,emmc45-ddr50-enabled");
212 	fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node,
213 			"fsp,emmc45-hs200-enabled");
214 	fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node,
215 			"fsp,emmc45-retune-timer-value", 8);
216 	fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd");
217 
218 	mem = &fsp_upd->memory_params;
219 	mem->enable_memory_down = fdtdec_get_bool(blob, node,
220 						  "fsp,enable-memory-down");
221 	if (mem->enable_memory_down) {
222 		node = fdtdec_next_compatible(blob, node,
223 					      COMPAT_INTEL_BAYTRAIL_FSP_MDP);
224 		if (node < 0) {
225 			debug("%s: Cannot find FSP memory-down-params node\n",
226 			      __func__);
227 		} else {
228 			mem->dram_speed = fdtdec_get_int(blob, node,
229 							 "fsp,dram-speed",
230 							 DRAM_SPEED_1333MTS);
231 			mem->dram_type = fdtdec_get_int(blob, node,
232 							"fsp,dram-type",
233 							DRAM_TYPE_DDR3L);
234 			mem->dimm_0_enable = fdtdec_get_bool(blob, node,
235 					"fsp,dimm-0-enable");
236 			mem->dimm_1_enable = fdtdec_get_bool(blob, node,
237 					"fsp,dimm-1-enable");
238 			mem->dimm_width = fdtdec_get_int(blob, node,
239 							 "fsp,dimm-width",
240 							 DIMM_WIDTH_X8);
241 			mem->dimm_density = fdtdec_get_int(blob, node,
242 							   "fsp,dimm-density",
243 							   DIMM_DENSITY_2GBIT);
244 			mem->dimm_bus_width = fdtdec_get_int(blob, node,
245 					"fsp,dimm-bus-width",
246 					DIMM_BUS_WIDTH_64BITS);
247 			mem->dimm_sides = fdtdec_get_int(blob, node,
248 							 "fsp,dimm-sides",
249 							 DIMM_SIDES_1RANKS);
250 			mem->dimm_tcl = fdtdec_get_int(blob, node,
251 						       "fsp,dimm-tcl", 0x09);
252 			mem->dimm_trpt_rcd = fdtdec_get_int(blob, node,
253 					"fsp,dimm-trpt-rcd", 0x09);
254 			mem->dimm_twr = fdtdec_get_int(blob, node,
255 						       "fsp,dimm-twr", 0x0a);
256 			mem->dimm_twtr = fdtdec_get_int(blob, node,
257 							"fsp,dimm-twtr", 0x05);
258 			mem->dimm_trrd = fdtdec_get_int(blob, node,
259 							"fsp,dimm-trrd", 0x04);
260 			mem->dimm_trtp = fdtdec_get_int(blob, node,
261 							"fsp,dimm-trtp", 0x05);
262 			mem->dimm_tfaw = fdtdec_get_int(blob, node,
263 							"fsp,dimm-tfaw", 0x14);
264 		}
265 	}
266 }
267