1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SUPPORT_SPL 36 select SPL 37 select SPL_SEPARATE_BSS 38 help 39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 40 experimental and many features are missing. U-Boot SPL starts up, 41 runs through the 16-bit and 32-bit init, then switches to 64-bit 42 mode and jumps to U-Boot proper. 43 44endchoice 45 46config X86_64 47 bool 48 49config SPL_X86_64 50 bool 51 depends on SPL 52 53choice 54 prompt "Mainboard vendor" 55 default VENDOR_EMULATION 56 57config VENDOR_ADVANTECH 58 bool "advantech" 59 60config VENDOR_CONGATEC 61 bool "congatec" 62 63config VENDOR_COREBOOT 64 bool "coreboot" 65 66config VENDOR_DFI 67 bool "dfi" 68 69config VENDOR_EFI 70 bool "efi" 71 72config VENDOR_EMULATION 73 bool "emulation" 74 75config VENDOR_GOOGLE 76 bool "Google" 77 78config VENDOR_INTEL 79 bool "Intel" 80 81endchoice 82 83# subarchitectures-specific options below 84config INTEL_MID 85 bool "Intel MID platform support" 86 help 87 Select to build a U-Boot capable of supporting Intel MID 88 (Mobile Internet Device) platform systems which do not have 89 the PCI legacy interfaces. 90 91 If you are building for a PC class system say N here. 92 93 Intel MID platforms are based on an Intel processor and 94 chipset which consume less power than most of the x86 95 derivatives. 96 97# board-specific options below 98source "board/advantech/Kconfig" 99source "board/congatec/Kconfig" 100source "board/coreboot/Kconfig" 101source "board/dfi/Kconfig" 102source "board/efi/Kconfig" 103source "board/emulation/Kconfig" 104source "board/google/Kconfig" 105source "board/intel/Kconfig" 106 107# platform-specific options below 108source "arch/x86/cpu/baytrail/Kconfig" 109source "arch/x86/cpu/broadwell/Kconfig" 110source "arch/x86/cpu/coreboot/Kconfig" 111source "arch/x86/cpu/ivybridge/Kconfig" 112source "arch/x86/cpu/qemu/Kconfig" 113source "arch/x86/cpu/quark/Kconfig" 114source "arch/x86/cpu/queensbay/Kconfig" 115 116# architecture-specific options below 117 118config AHCI 119 default y 120 121config SYS_MALLOC_F_LEN 122 default 0x800 123 124config RAMBASE 125 hex 126 default 0x100000 127 128config XIP_ROM_SIZE 129 hex 130 depends on X86_RESET_VECTOR 131 default ROM_SIZE 132 133config CPU_ADDR_BITS 134 int 135 default 36 136 137config HPET_ADDRESS 138 hex 139 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 140 141config SMM_TSEG 142 bool 143 default n 144 145config SMM_TSEG_SIZE 146 hex 147 148config X86_RESET_VECTOR 149 bool 150 default n 151 152# The following options control where the 16-bit and 32-bit init lies 153# If SPL is enabled then it normally holds this init code, and U-Boot proper 154# is normally a 64-bit build. 155# 156# The 16-bit init refers to the reset vector and the small amount of code to 157# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 158# or missing altogether if U-Boot is started from EFI or coreboot. 159# 160# The 32-bit init refers to processor init, running binary blobs including 161# FSP, setting up interrupts and anything else that needs to be done in 162# 32-bit code. It is normally in the same place as 16-bit init if that is 163# enabled (i.e. they are both in SPL, or both in U-Boot proper). 164config X86_16BIT_INIT 165 bool 166 depends on X86_RESET_VECTOR 167 default y if X86_RESET_VECTOR && !SPL 168 help 169 This is enabled when 16-bit init is in U-Boot proper 170 171config SPL_X86_16BIT_INIT 172 bool 173 depends on X86_RESET_VECTOR 174 default y if X86_RESET_VECTOR && SPL 175 help 176 This is enabled when 16-bit init is in SPL 177 178config X86_32BIT_INIT 179 bool 180 depends on X86_RESET_VECTOR 181 default y if X86_RESET_VECTOR && !SPL 182 help 183 This is enabled when 32-bit init is in U-Boot proper 184 185config SPL_X86_32BIT_INIT 186 bool 187 depends on X86_RESET_VECTOR 188 default y if X86_RESET_VECTOR && SPL 189 help 190 This is enabled when 32-bit init is in SPL 191 192config RESET_SEG_START 193 hex 194 depends on X86_RESET_VECTOR 195 default 0xffff0000 196 197config RESET_SEG_SIZE 198 hex 199 depends on X86_RESET_VECTOR 200 default 0x10000 201 202config RESET_VEC_LOC 203 hex 204 depends on X86_RESET_VECTOR 205 default 0xfffffff0 206 207config SYS_X86_START16 208 hex 209 depends on X86_RESET_VECTOR 210 default 0xfffff800 211 212config X86_LOAD_FROM_32_BIT 213 bool "Boot from a 32-bit program" 214 help 215 Define this to boot U-Boot from a 32-bit program which sets 216 the GDT differently. This can be used to boot directly from 217 any stage of coreboot, for example, bypassing the normal 218 payload-loading feature. 219 220config BOARD_ROMSIZE_KB_512 221 bool 222config BOARD_ROMSIZE_KB_1024 223 bool 224config BOARD_ROMSIZE_KB_2048 225 bool 226config BOARD_ROMSIZE_KB_4096 227 bool 228config BOARD_ROMSIZE_KB_8192 229 bool 230config BOARD_ROMSIZE_KB_16384 231 bool 232 233choice 234 prompt "ROM chip size" 235 depends on X86_RESET_VECTOR 236 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 237 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 238 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 239 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 240 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 241 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 242 help 243 Select the size of the ROM chip you intend to flash U-Boot on. 244 245 The build system will take care of creating a u-boot.rom file 246 of the matching size. 247 248config UBOOT_ROMSIZE_KB_512 249 bool "512 KB" 250 help 251 Choose this option if you have a 512 KB ROM chip. 252 253config UBOOT_ROMSIZE_KB_1024 254 bool "1024 KB (1 MB)" 255 help 256 Choose this option if you have a 1024 KB (1 MB) ROM chip. 257 258config UBOOT_ROMSIZE_KB_2048 259 bool "2048 KB (2 MB)" 260 help 261 Choose this option if you have a 2048 KB (2 MB) ROM chip. 262 263config UBOOT_ROMSIZE_KB_4096 264 bool "4096 KB (4 MB)" 265 help 266 Choose this option if you have a 4096 KB (4 MB) ROM chip. 267 268config UBOOT_ROMSIZE_KB_8192 269 bool "8192 KB (8 MB)" 270 help 271 Choose this option if you have a 8192 KB (8 MB) ROM chip. 272 273config UBOOT_ROMSIZE_KB_16384 274 bool "16384 KB (16 MB)" 275 help 276 Choose this option if you have a 16384 KB (16 MB) ROM chip. 277 278endchoice 279 280# Map the config names to an integer (KB). 281config UBOOT_ROMSIZE_KB 282 int 283 default 512 if UBOOT_ROMSIZE_KB_512 284 default 1024 if UBOOT_ROMSIZE_KB_1024 285 default 2048 if UBOOT_ROMSIZE_KB_2048 286 default 4096 if UBOOT_ROMSIZE_KB_4096 287 default 8192 if UBOOT_ROMSIZE_KB_8192 288 default 16384 if UBOOT_ROMSIZE_KB_16384 289 290# Map the config names to a hex value (bytes). 291config ROM_SIZE 292 hex 293 default 0x80000 if UBOOT_ROMSIZE_KB_512 294 default 0x100000 if UBOOT_ROMSIZE_KB_1024 295 default 0x200000 if UBOOT_ROMSIZE_KB_2048 296 default 0x400000 if UBOOT_ROMSIZE_KB_4096 297 default 0x800000 if UBOOT_ROMSIZE_KB_8192 298 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 299 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 300 301config HAVE_INTEL_ME 302 bool "Platform requires Intel Management Engine" 303 help 304 Newer higher-end devices have an Intel Management Engine (ME) 305 which is a very large binary blob (typically 1.5MB) which is 306 required for the platform to work. This enforces a particular 307 SPI flash format. You will need to supply the me.bin file in 308 your board directory. 309 310config X86_RAMTEST 311 bool "Perform a simple RAM test after SDRAM initialisation" 312 help 313 If there is something wrong with SDRAM then the platform will 314 often crash within U-Boot or the kernel. This option enables a 315 very simple RAM test that quickly checks whether the SDRAM seems 316 to work correctly. It is not exhaustive but can save time by 317 detecting obvious failures. 318 319config HAVE_FSP 320 bool "Add an Firmware Support Package binary" 321 depends on !EFI 322 help 323 Select this option to add an Firmware Support Package binary to 324 the resulting U-Boot image. It is a binary blob which U-Boot uses 325 to set up SDRAM and other chipset specific initialization. 326 327 Note: Without this binary U-Boot will not be able to set up its 328 SDRAM so will not boot. 329 330config FSP_FILE 331 string "Firmware Support Package binary filename" 332 depends on HAVE_FSP 333 default "fsp.bin" 334 help 335 The filename of the file to use as Firmware Support Package binary 336 in the board directory. 337 338config FSP_ADDR 339 hex "Firmware Support Package binary location" 340 depends on HAVE_FSP 341 default 0xfffc0000 342 help 343 FSP is not Position Independent Code (PIC) and the whole FSP has to 344 be rebased if it is placed at a location which is different from the 345 perferred base address specified during the FSP build. Use Intel's 346 Binary Configuration Tool (BCT) to do the rebase. 347 348 The default base address of 0xfffc0000 indicates that the binary must 349 be located at offset 0xc0000 from the beginning of a 1MB flash device. 350 351config FSP_TEMP_RAM_ADDR 352 hex 353 depends on HAVE_FSP 354 default 0x2000000 355 help 356 Stack top address which is used in fsp_init() after DRAM is ready and 357 CAR is disabled. 358 359config FSP_SYS_MALLOC_F_LEN 360 hex 361 depends on HAVE_FSP 362 default 0x100000 363 help 364 Additional size of malloc() pool before relocation. 365 366config FSP_USE_UPD 367 bool 368 depends on HAVE_FSP 369 default y 370 help 371 Most FSPs use UPD data region for some FSP customization. But there 372 are still some FSPs that might not even have UPD. For such FSPs, 373 override this to n in their platform Kconfig files. 374 375config FSP_BROKEN_HOB 376 bool 377 depends on HAVE_FSP 378 help 379 Indicate some buggy FSPs that does not report memory used by FSP 380 itself as reserved in the resource descriptor HOB. Select this to 381 tell U-Boot to do some additional work to ensure U-Boot relocation 382 do not overwrite the important boot service data which is used by 383 FSP, otherwise the subsequent call to fsp_notify() will fail. 384 385config ENABLE_MRC_CACHE 386 bool "Enable MRC cache" 387 depends on !EFI && !SYS_COREBOOT 388 help 389 Enable this feature to cause MRC data to be cached in NV storage 390 to be used for speeding up boot time on future reboots and/or 391 power cycles. 392 393 For platforms that use Intel FSP for the memory initialization, 394 please check FSP output HOB via U-Boot command 'fsp hob' to see 395 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 396 If such GUID does not exist, MRC cache is not avaiable on such 397 platform (eg: Intel Queensbay), which means selecting this option 398 here does not make any difference. 399 400config HAVE_MRC 401 bool "Add a System Agent binary" 402 depends on !HAVE_FSP 403 help 404 Select this option to add a System Agent binary to 405 the resulting U-Boot image. MRC stands for Memory Reference Code. 406 It is a binary blob which U-Boot uses to set up SDRAM. 407 408 Note: Without this binary U-Boot will not be able to set up its 409 SDRAM so will not boot. 410 411config CACHE_MRC_BIN 412 bool 413 depends on HAVE_MRC 414 default n 415 help 416 Enable caching for the memory reference code binary. This uses an 417 MTRR (memory type range register) to turn on caching for the section 418 of SPI flash that contains the memory reference code. This makes 419 SDRAM init run faster. 420 421config CACHE_MRC_SIZE_KB 422 int 423 depends on HAVE_MRC 424 default 512 425 help 426 Sets the size of the cached area for the memory reference code. 427 This ends at the end of SPI flash (address 0xffffffff) and is 428 measured in KB. Typically this is set to 512, providing for 0.5MB 429 of cached space. 430 431config DCACHE_RAM_BASE 432 hex 433 depends on HAVE_MRC 434 help 435 Sets the base of the data cache area in memory space. This is the 436 start address of the cache-as-RAM (CAR) area and the address varies 437 depending on the CPU. Once CAR is set up, read/write memory becomes 438 available at this address and can be used temporarily until SDRAM 439 is working. 440 441config DCACHE_RAM_SIZE 442 hex 443 depends on HAVE_MRC 444 default 0x40000 445 help 446 Sets the total size of the data cache area in memory space. This 447 sets the size of the cache-as-RAM (CAR) area. Note that much of the 448 CAR space is required by the MRC. The CAR space available to U-Boot 449 is normally at the start and typically extends to 1/4 or 1/2 of the 450 available size. 451 452config DCACHE_RAM_MRC_VAR_SIZE 453 hex 454 depends on HAVE_MRC 455 help 456 This is the amount of CAR (Cache as RAM) reserved for use by the 457 memory reference code. This depends on the implementation of the 458 memory reference code and must be set correctly or the board will 459 not boot. 460 461config HAVE_REFCODE 462 bool "Add a Reference Code binary" 463 help 464 Select this option to add a Reference Code binary to the resulting 465 U-Boot image. This is an Intel binary blob that handles system 466 initialisation, in this case the PCH and System Agent. 467 468 Note: Without this binary (on platforms that need it such as 469 broadwell) U-Boot will be missing some critical setup steps. 470 Various peripherals may fail to work. 471 472config SMP 473 bool "Enable Symmetric Multiprocessing" 474 default n 475 help 476 Enable use of more than one CPU in U-Boot and the Operating System 477 when loaded. Each CPU will be started up and information can be 478 obtained using the 'cpu' command. If this option is disabled, then 479 only one CPU will be enabled regardless of the number of CPUs 480 available. 481 482config MAX_CPUS 483 int "Maximum number of CPUs permitted" 484 depends on SMP 485 default 4 486 help 487 When using multi-CPU chips it is possible for U-Boot to start up 488 more than one CPU. The stack memory used by all of these CPUs is 489 pre-allocated so at present U-Boot wants to know the maximum 490 number of CPUs that may be present. Set this to at least as high 491 as the number of CPUs in your system (it uses about 4KB of RAM for 492 each CPU). 493 494config AP_STACK_SIZE 495 hex 496 depends on SMP 497 default 0x1000 498 help 499 Each additional CPU started by U-Boot requires its own stack. This 500 option sets the stack size used by each CPU and directly affects 501 the memory used by this initialisation process. Typically 4KB is 502 enough space. 503 504config HAVE_VGA_BIOS 505 bool "Add a VGA BIOS image" 506 help 507 Select this option if you have a VGA BIOS image that you would 508 like to add to your ROM. 509 510config VGA_BIOS_FILE 511 string "VGA BIOS image filename" 512 depends on HAVE_VGA_BIOS 513 default "vga.bin" 514 help 515 The filename of the VGA BIOS image in the board directory. 516 517config VGA_BIOS_ADDR 518 hex "VGA BIOS image location" 519 depends on HAVE_VGA_BIOS 520 default 0xfff90000 521 help 522 The location of VGA BIOS image in the SPI flash. For example, base 523 address of 0xfff90000 indicates that the image will be put at offset 524 0x90000 from the beginning of a 1MB flash device. 525 526menu "System tables" 527 depends on !EFI && !SYS_COREBOOT 528 529config GENERATE_PIRQ_TABLE 530 bool "Generate a PIRQ table" 531 default n 532 help 533 Generate a PIRQ routing table for this board. The PIRQ routing table 534 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 535 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 536 It specifies the interrupt router information as well how all the PCI 537 devices' interrupt pins are wired to PIRQs. 538 539config GENERATE_SFI_TABLE 540 bool "Generate a SFI (Simple Firmware Interface) table" 541 help 542 The Simple Firmware Interface (SFI) provides a lightweight method 543 for platform firmware to pass information to the operating system 544 via static tables in memory. Kernel SFI support is required to 545 boot on SFI-only platforms. If you have ACPI tables then these are 546 used instead. 547 548 U-Boot writes this table in write_sfi_table() just before booting 549 the OS. 550 551 For more information, see http://simplefirmware.org 552 553config GENERATE_MP_TABLE 554 bool "Generate an MP (Multi-Processor) table" 555 default n 556 help 557 Generate an MP (Multi-Processor) table for this board. The MP table 558 provides a way for the operating system to support for symmetric 559 multiprocessing as well as symmetric I/O interrupt handling with 560 the local APIC and I/O APIC. 561 562config GENERATE_ACPI_TABLE 563 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 564 default n 565 select QFW if QEMU 566 help 567 The Advanced Configuration and Power Interface (ACPI) specification 568 provides an open standard for device configuration and management 569 by the operating system. It defines platform-independent interfaces 570 for configuration and power management monitoring. 571 572endmenu 573 574config MAX_PIRQ_LINKS 575 int 576 default 8 577 help 578 This variable specifies the number of PIRQ interrupt links which are 579 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 580 Some newer chipsets offer more than four links, commonly up to PIRQH. 581 582config IRQ_SLOT_COUNT 583 int 584 default 128 585 help 586 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 587 which in turns forms a table of exact 4KiB. The default value 128 588 should be enough for most boards. If this does not fit your board, 589 change it according to your needs. 590 591config PCIE_ECAM_BASE 592 hex 593 default 0xe0000000 594 help 595 This is the memory-mapped address of PCI configuration space, which 596 is only available through the Enhanced Configuration Access 597 Mechanism (ECAM) with PCI Express. It can be set up almost 598 anywhere. Before it is set up, it is possible to access PCI 599 configuration space through I/O access, but memory access is more 600 convenient. Using this, PCI can be scanned and configured. This 601 should be set to a region that does not conflict with memory 602 assigned to PCI devices - i.e. the memory and prefetch regions, as 603 passed to pci_set_region(). 604 605config PCIE_ECAM_SIZE 606 hex 607 default 0x10000000 608 help 609 This is the size of memory-mapped address of PCI configuration space, 610 which is only available through the Enhanced Configuration Access 611 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 612 so a default 0x10000000 size covers all of the 256 buses which is the 613 maximum number of PCI buses as defined by the PCI specification. 614 615config I8259_PIC 616 bool 617 default y 618 help 619 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 620 slave) interrupt controllers. Include this to have U-Boot set up 621 the interrupt correctly. 622 623config I8254_TIMER 624 bool 625 default y 626 help 627 Intel 8254 timer contains three counters which have fixed uses. 628 Include this to have U-Boot set up the timer correctly. 629 630config SEABIOS 631 bool "Support booting SeaBIOS" 632 help 633 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 634 It can run in an emulator or natively on X86 hardware with the use 635 of coreboot/U-Boot. By turning on this option, U-Boot prepares 636 all the configuration tables that are necessary to boot SeaBIOS. 637 638 Check http://www.seabios.org/SeaBIOS for details. 639 640config HIGH_TABLE_SIZE 641 hex "Size of configuration tables which reside in high memory" 642 default 0x10000 643 depends on SEABIOS 644 help 645 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 646 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 647 puts a copy of configuration tables in high memory region which 648 is reserved on the stack before relocation. The region size is 649 determined by this option. 650 651 Increse it if the default size does not fit the board's needs. 652 This is most likely due to a large ACPI DSDT table is used. 653 654source "arch/x86/lib/efi/Kconfig" 655 656endmenu 657