xref: /openbmc/u-boot/arch/x86/Kconfig (revision cc7debc7) 
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7config USE_PRIVATE_LIBGCC
8	default y
9
10config SYS_VSNPRINTF
11	default y
12
13choice
14	prompt "Mainboard vendor"
15	default VENDOR_EMULATION
16
17config VENDOR_COREBOOT
18	bool "coreboot"
19
20config VENDOR_EMULATION
21	bool "emulation"
22
23config VENDOR_GOOGLE
24	bool "Google"
25
26config VENDOR_INTEL
27	bool "Intel"
28
29endchoice
30
31# board-specific options below
32source "board/coreboot/Kconfig"
33source "board/emulation/Kconfig"
34source "board/google/Kconfig"
35source "board/intel/Kconfig"
36
37# platform-specific options below
38source "arch/x86/cpu/baytrail/Kconfig"
39source "arch/x86/cpu/coreboot/Kconfig"
40source "arch/x86/cpu/ivybridge/Kconfig"
41source "arch/x86/cpu/qemu/Kconfig"
42source "arch/x86/cpu/quark/Kconfig"
43source "arch/x86/cpu/queensbay/Kconfig"
44
45# architecture-specific options below
46
47config SYS_MALLOC_F_LEN
48	default 0x800
49
50config RAMBASE
51	hex
52	default 0x100000
53
54config XIP_ROM_SIZE
55	hex
56	depends on X86_RESET_VECTOR
57	default ROM_SIZE
58
59config CPU_ADDR_BITS
60	int
61	default 36
62
63config HPET_ADDRESS
64	hex
65	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
66
67config SMM_TSEG
68	bool
69	default n
70
71config SMM_TSEG_SIZE
72	hex
73
74config X86_RESET_VECTOR
75	bool
76	default n
77
78config SYS_X86_START16
79	hex
80	depends on X86_RESET_VECTOR
81	default 0xfffff800
82
83config BOARD_ROMSIZE_KB_512
84	bool
85config BOARD_ROMSIZE_KB_1024
86	bool
87config BOARD_ROMSIZE_KB_2048
88	bool
89config BOARD_ROMSIZE_KB_4096
90	bool
91config BOARD_ROMSIZE_KB_8192
92	bool
93config BOARD_ROMSIZE_KB_16384
94	bool
95
96choice
97	prompt "ROM chip size"
98	depends on X86_RESET_VECTOR
99	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
100	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
101	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
102	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
103	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
104	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
105	help
106	  Select the size of the ROM chip you intend to flash U-Boot on.
107
108	  The build system will take care of creating a u-boot.rom file
109	  of the matching size.
110
111config UBOOT_ROMSIZE_KB_512
112	bool "512 KB"
113	help
114	  Choose this option if you have a 512 KB ROM chip.
115
116config UBOOT_ROMSIZE_KB_1024
117	bool "1024 KB (1 MB)"
118	help
119	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
120
121config UBOOT_ROMSIZE_KB_2048
122	bool "2048 KB (2 MB)"
123	help
124	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
125
126config UBOOT_ROMSIZE_KB_4096
127	bool "4096 KB (4 MB)"
128	help
129	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
130
131config UBOOT_ROMSIZE_KB_8192
132	bool "8192 KB (8 MB)"
133	help
134	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
135
136config UBOOT_ROMSIZE_KB_16384
137	bool "16384 KB (16 MB)"
138	help
139	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
140
141endchoice
142
143# Map the config names to an integer (KB).
144config UBOOT_ROMSIZE_KB
145	int
146	default 512 if UBOOT_ROMSIZE_KB_512
147	default 1024 if UBOOT_ROMSIZE_KB_1024
148	default 2048 if UBOOT_ROMSIZE_KB_2048
149	default 4096 if UBOOT_ROMSIZE_KB_4096
150	default 8192 if UBOOT_ROMSIZE_KB_8192
151	default 16384 if UBOOT_ROMSIZE_KB_16384
152
153# Map the config names to a hex value (bytes).
154config ROM_SIZE
155	hex
156	default 0x80000 if UBOOT_ROMSIZE_KB_512
157	default 0x100000 if UBOOT_ROMSIZE_KB_1024
158	default 0x200000 if UBOOT_ROMSIZE_KB_2048
159	default 0x400000 if UBOOT_ROMSIZE_KB_4096
160	default 0x800000 if UBOOT_ROMSIZE_KB_8192
161	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
162	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
163
164config HAVE_INTEL_ME
165	bool "Platform requires Intel Management Engine"
166	help
167	  Newer higher-end devices have an Intel Management Engine (ME)
168	  which is a very large binary blob (typically 1.5MB) which is
169	  required for the platform to work. This enforces a particular
170	  SPI flash format. You will need to supply the me.bin file in
171	  your board directory.
172
173config X86_RAMTEST
174	bool "Perform a simple RAM test after SDRAM initialisation"
175	help
176	  If there is something wrong with SDRAM then the platform will
177	  often crash within U-Boot or the kernel. This option enables a
178	  very simple RAM test that quickly checks whether the SDRAM seems
179	  to work correctly. It is not exhaustive but can save time by
180	  detecting obvious failures.
181
182config MARK_GRAPHICS_MEM_WRCOMB
183	bool "Mark graphics memory as write-combining"
184	default n
185	help
186	  The graphics performance may increase if the graphics
187	  memory is set as write-combining cache type. This option
188	  enables marking the graphics memory as write-combining.
189
190config HAVE_FSP
191	bool "Add an Firmware Support Package binary"
192	help
193	  Select this option to add an Firmware Support Package binary to
194	  the resulting U-Boot image. It is a binary blob which U-Boot uses
195	  to set up SDRAM and other chipset specific initialization.
196
197	  Note: Without this binary U-Boot will not be able to set up its
198	  SDRAM so will not boot.
199
200config FSP_FILE
201	string "Firmware Support Package binary filename"
202	depends on HAVE_FSP
203	default "fsp.bin"
204	help
205	  The filename of the file to use as Firmware Support Package binary
206	  in the board directory.
207
208config FSP_ADDR
209	hex "Firmware Support Package binary location"
210	depends on HAVE_FSP
211	default 0xfffc0000
212	help
213	  FSP is not Position Independent Code (PIC) and the whole FSP has to
214	  be rebased if it is placed at a location which is different from the
215	  perferred base address specified during the FSP build. Use Intel's
216	  Binary Configuration Tool (BCT) to do the rebase.
217
218	  The default base address of 0xfffc0000 indicates that the binary must
219	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
220
221config FSP_TEMP_RAM_ADDR
222	hex
223	default 0x2000000
224	help
225	  Stack top address which is used in FspInit after DRAM is ready and
226	  CAR is disabled.
227
228config MAX_CPUS
229        int "Maximum number of CPUs permitted"
230        default 4
231        help
232          When using multi-CPU chips it is possible for U-Boot to start up
233          more than one CPU. The stack memory used by all of these CPUs is
234          pre-allocated so at present U-Boot wants to know the maximum
235          number of CPUs that may be present. Set this to at least as high
236          as the number of CPUs in your system (it uses about 4KB of RAM for
237          each CPU).
238
239config SMP
240	bool "Enable Symmetric Multiprocessing"
241	default n
242	help
243	  Enable use of more than one CPU in U-Boot and the Operating System
244	  when loaded. Each CPU will be started up and information can be
245	  obtained using the 'cpu' command. If this option is disabled, then
246	  only one CPU will be enabled regardless of the number of CPUs
247	  available.
248
249config AP_STACK_SIZE
250	hex
251	default 0x1000
252	help
253	  Each additional CPU started by U-Boot requires its own stack. This
254	  option sets the stack size used by each CPU and directly affects
255	  the memory used by this initialisation process. Typically 4KB is
256	  enough space.
257
258config TSC_CALIBRATION_BYPASS
259	bool "Bypass Time-Stamp Counter (TSC) calibration"
260	default n
261	help
262	  By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
263	  running frequency via Model-Specific Register (MSR) and Programmable
264	  Interval Timer (PIT). If the calibration does not work on your board,
265	  select this option and provide a hardcoded TSC running frequency with
266	  CONFIG_TSC_FREQ_IN_MHZ below.
267
268	  Normally this option should be turned on in a simulation environment
269	  like qemu.
270
271config TSC_FREQ_IN_MHZ
272	int "Time-Stamp Counter (TSC) running frequency in MHz"
273	depends on TSC_CALIBRATION_BYPASS
274	default 1000
275	help
276	  The running frequency in MHz of Time-Stamp Counter (TSC).
277
278menu "System tables"
279
280config GENERATE_PIRQ_TABLE
281	bool "Generate a PIRQ table"
282	default n
283	help
284	  Generate a PIRQ routing table for this board. The PIRQ routing table
285	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
286	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
287	  It specifies the interrupt router information as well how all the PCI
288	  devices' interrupt pins are wired to PIRQs.
289
290config GENERATE_SFI_TABLE
291	bool "Generate a SFI (Simple Firmware Interface) table"
292	help
293	  The Simple Firmware Interface (SFI) provides a lightweight method
294	  for platform firmware to pass information to the operating system
295	  via static tables in memory.  Kernel SFI support is required to
296	  boot on SFI-only platforms.  If you have ACPI tables then these are
297	  used instead.
298
299	  U-Boot writes this table in write_sfi_table() just before booting
300	  the OS.
301
302	  For more information, see http://simplefirmware.org
303
304endmenu
305
306config MAX_PIRQ_LINKS
307	int
308	default 8
309	help
310	  This variable specifies the number of PIRQ interrupt links which are
311	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
312	  Some newer chipsets offer more than four links, commonly up to PIRQH.
313
314config IRQ_SLOT_COUNT
315	int
316	default 128
317	help
318	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
319	  which in turns forms a table of exact 4KiB. The default value 128
320	  should be enough for most boards. If this does not fit your board,
321	  change it according to your needs.
322
323config PCIE_ECAM_BASE
324	hex
325	default 0xe0000000
326	help
327	  This is the memory-mapped address of PCI configuration space, which
328	  is only available through the Enhanced Configuration Access
329	  Mechanism (ECAM) with PCI Express. It can be set up almost
330	  anywhere. Before it is set up, it is possible to access PCI
331	  configuration space through I/O access, but memory access is more
332	  convenient. Using this, PCI can be scanned and configured. This
333	  should be set to a region that does not conflict with memory
334	  assigned to PCI devices - i.e. the memory and prefetch regions, as
335	  passed to pci_set_region().
336
337config BOOTSTAGE
338	default y
339
340config BOOTSTAGE_REPORT
341	default y
342
343config CMD_BOOTSTAGE
344	default y
345
346endmenu
347