1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SUPPORT_SPL 36 select SPL 37 select SPL_SEPARATE_BSS 38 help 39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 40 experimental and many features are missing. U-Boot SPL starts up, 41 runs through the 16-bit and 32-bit init, then switches to 64-bit 42 mode and jumps to U-Boot proper. 43 44endchoice 45 46config X86_64 47 bool 48 49config SPL_X86_64 50 bool 51 depends on SPL 52 53choice 54 prompt "Mainboard vendor" 55 default VENDOR_EMULATION 56 57config VENDOR_ADVANTECH 58 bool "advantech" 59 60config VENDOR_CONGATEC 61 bool "congatec" 62 63config VENDOR_COREBOOT 64 bool "coreboot" 65 66config VENDOR_DFI 67 bool "dfi" 68 69config VENDOR_EFI 70 bool "efi" 71 72config VENDOR_EMULATION 73 bool "emulation" 74 75config VENDOR_GOOGLE 76 bool "Google" 77 78config VENDOR_INTEL 79 bool "Intel" 80 81endchoice 82 83# board-specific options below 84source "board/advantech/Kconfig" 85source "board/congatec/Kconfig" 86source "board/coreboot/Kconfig" 87source "board/dfi/Kconfig" 88source "board/efi/Kconfig" 89source "board/emulation/Kconfig" 90source "board/google/Kconfig" 91source "board/intel/Kconfig" 92 93# platform-specific options below 94source "arch/x86/cpu/baytrail/Kconfig" 95source "arch/x86/cpu/broadwell/Kconfig" 96source "arch/x86/cpu/coreboot/Kconfig" 97source "arch/x86/cpu/ivybridge/Kconfig" 98source "arch/x86/cpu/qemu/Kconfig" 99source "arch/x86/cpu/quark/Kconfig" 100source "arch/x86/cpu/queensbay/Kconfig" 101 102# architecture-specific options below 103 104config AHCI 105 default y 106 107config SYS_MALLOC_F_LEN 108 default 0x800 109 110config RAMBASE 111 hex 112 default 0x100000 113 114config XIP_ROM_SIZE 115 hex 116 depends on X86_RESET_VECTOR 117 default ROM_SIZE 118 119config CPU_ADDR_BITS 120 int 121 default 36 122 123config HPET_ADDRESS 124 hex 125 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 126 127config SMM_TSEG 128 bool 129 default n 130 131config SMM_TSEG_SIZE 132 hex 133 134config X86_RESET_VECTOR 135 bool 136 default n 137 138# The following options control where the 16-bit and 32-bit init lies 139# If SPL is enabled then it normally holds this init code, and U-Boot proper 140# is normally a 64-bit build. 141# 142# The 16-bit init refers to the reset vector and the small amount of code to 143# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 144# or missing altogether if U-Boot is started from EFI or coreboot. 145# 146# The 32-bit init refers to processor init, running binary blobs including 147# FSP, setting up interrupts and anything else that needs to be done in 148# 32-bit code. It is normally in the same place as 16-bit init if that is 149# enabled (i.e. they are both in SPL, or both in U-Boot proper). 150config X86_16BIT_INIT 151 bool 152 depends on X86_RESET_VECTOR 153 default y if X86_RESET_VECTOR && !SPL 154 help 155 This is enabled when 16-bit init is in U-Boot proper 156 157config SPL_X86_16BIT_INIT 158 bool 159 depends on X86_RESET_VECTOR 160 default y if X86_RESET_VECTOR && SPL 161 help 162 This is enabled when 16-bit init is in SPL 163 164config X86_32BIT_INIT 165 bool 166 depends on X86_RESET_VECTOR 167 default y if X86_RESET_VECTOR && !SPL 168 help 169 This is enabled when 32-bit init is in U-Boot proper 170 171config SPL_X86_32BIT_INIT 172 bool 173 depends on X86_RESET_VECTOR 174 default y if X86_RESET_VECTOR && SPL 175 help 176 This is enabled when 32-bit init is in SPL 177 178config RESET_SEG_START 179 hex 180 depends on X86_RESET_VECTOR 181 default 0xffff0000 182 183config RESET_SEG_SIZE 184 hex 185 depends on X86_RESET_VECTOR 186 default 0x10000 187 188config RESET_VEC_LOC 189 hex 190 depends on X86_RESET_VECTOR 191 default 0xfffffff0 192 193config SYS_X86_START16 194 hex 195 depends on X86_RESET_VECTOR 196 default 0xfffff800 197 198config X86_LOAD_FROM_32_BIT 199 bool "Boot from a 32-bit program" 200 help 201 Define this to boot U-Boot from a 32-bit program which sets 202 the GDT differently. This can be used to boot directly from 203 any stage of coreboot, for example, bypassing the normal 204 payload-loading feature. 205 206config BOARD_ROMSIZE_KB_512 207 bool 208config BOARD_ROMSIZE_KB_1024 209 bool 210config BOARD_ROMSIZE_KB_2048 211 bool 212config BOARD_ROMSIZE_KB_4096 213 bool 214config BOARD_ROMSIZE_KB_8192 215 bool 216config BOARD_ROMSIZE_KB_16384 217 bool 218 219choice 220 prompt "ROM chip size" 221 depends on X86_RESET_VECTOR 222 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 223 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 224 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 225 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 226 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 227 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 228 help 229 Select the size of the ROM chip you intend to flash U-Boot on. 230 231 The build system will take care of creating a u-boot.rom file 232 of the matching size. 233 234config UBOOT_ROMSIZE_KB_512 235 bool "512 KB" 236 help 237 Choose this option if you have a 512 KB ROM chip. 238 239config UBOOT_ROMSIZE_KB_1024 240 bool "1024 KB (1 MB)" 241 help 242 Choose this option if you have a 1024 KB (1 MB) ROM chip. 243 244config UBOOT_ROMSIZE_KB_2048 245 bool "2048 KB (2 MB)" 246 help 247 Choose this option if you have a 2048 KB (2 MB) ROM chip. 248 249config UBOOT_ROMSIZE_KB_4096 250 bool "4096 KB (4 MB)" 251 help 252 Choose this option if you have a 4096 KB (4 MB) ROM chip. 253 254config UBOOT_ROMSIZE_KB_8192 255 bool "8192 KB (8 MB)" 256 help 257 Choose this option if you have a 8192 KB (8 MB) ROM chip. 258 259config UBOOT_ROMSIZE_KB_16384 260 bool "16384 KB (16 MB)" 261 help 262 Choose this option if you have a 16384 KB (16 MB) ROM chip. 263 264endchoice 265 266# Map the config names to an integer (KB). 267config UBOOT_ROMSIZE_KB 268 int 269 default 512 if UBOOT_ROMSIZE_KB_512 270 default 1024 if UBOOT_ROMSIZE_KB_1024 271 default 2048 if UBOOT_ROMSIZE_KB_2048 272 default 4096 if UBOOT_ROMSIZE_KB_4096 273 default 8192 if UBOOT_ROMSIZE_KB_8192 274 default 16384 if UBOOT_ROMSIZE_KB_16384 275 276# Map the config names to a hex value (bytes). 277config ROM_SIZE 278 hex 279 default 0x80000 if UBOOT_ROMSIZE_KB_512 280 default 0x100000 if UBOOT_ROMSIZE_KB_1024 281 default 0x200000 if UBOOT_ROMSIZE_KB_2048 282 default 0x400000 if UBOOT_ROMSIZE_KB_4096 283 default 0x800000 if UBOOT_ROMSIZE_KB_8192 284 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 285 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 286 287config HAVE_INTEL_ME 288 bool "Platform requires Intel Management Engine" 289 help 290 Newer higher-end devices have an Intel Management Engine (ME) 291 which is a very large binary blob (typically 1.5MB) which is 292 required for the platform to work. This enforces a particular 293 SPI flash format. You will need to supply the me.bin file in 294 your board directory. 295 296config X86_RAMTEST 297 bool "Perform a simple RAM test after SDRAM initialisation" 298 help 299 If there is something wrong with SDRAM then the platform will 300 often crash within U-Boot or the kernel. This option enables a 301 very simple RAM test that quickly checks whether the SDRAM seems 302 to work correctly. It is not exhaustive but can save time by 303 detecting obvious failures. 304 305config HAVE_FSP 306 bool "Add an Firmware Support Package binary" 307 depends on !EFI 308 help 309 Select this option to add an Firmware Support Package binary to 310 the resulting U-Boot image. It is a binary blob which U-Boot uses 311 to set up SDRAM and other chipset specific initialization. 312 313 Note: Without this binary U-Boot will not be able to set up its 314 SDRAM so will not boot. 315 316config FSP_FILE 317 string "Firmware Support Package binary filename" 318 depends on HAVE_FSP 319 default "fsp.bin" 320 help 321 The filename of the file to use as Firmware Support Package binary 322 in the board directory. 323 324config FSP_ADDR 325 hex "Firmware Support Package binary location" 326 depends on HAVE_FSP 327 default 0xfffc0000 328 help 329 FSP is not Position Independent Code (PIC) and the whole FSP has to 330 be rebased if it is placed at a location which is different from the 331 perferred base address specified during the FSP build. Use Intel's 332 Binary Configuration Tool (BCT) to do the rebase. 333 334 The default base address of 0xfffc0000 indicates that the binary must 335 be located at offset 0xc0000 from the beginning of a 1MB flash device. 336 337config FSP_TEMP_RAM_ADDR 338 hex 339 depends on HAVE_FSP 340 default 0x2000000 341 help 342 Stack top address which is used in fsp_init() after DRAM is ready and 343 CAR is disabled. 344 345config FSP_SYS_MALLOC_F_LEN 346 hex 347 depends on HAVE_FSP 348 default 0x100000 349 help 350 Additional size of malloc() pool before relocation. 351 352config FSP_USE_UPD 353 bool 354 depends on HAVE_FSP 355 default y 356 help 357 Most FSPs use UPD data region for some FSP customization. But there 358 are still some FSPs that might not even have UPD. For such FSPs, 359 override this to n in their platform Kconfig files. 360 361config FSP_BROKEN_HOB 362 bool 363 depends on HAVE_FSP 364 help 365 Indicate some buggy FSPs that does not report memory used by FSP 366 itself as reserved in the resource descriptor HOB. Select this to 367 tell U-Boot to do some additional work to ensure U-Boot relocation 368 do not overwrite the important boot service data which is used by 369 FSP, otherwise the subsequent call to fsp_notify() will fail. 370 371config ENABLE_MRC_CACHE 372 bool "Enable MRC cache" 373 depends on !EFI && !SYS_COREBOOT 374 help 375 Enable this feature to cause MRC data to be cached in NV storage 376 to be used for speeding up boot time on future reboots and/or 377 power cycles. 378 379 For platforms that use Intel FSP for the memory initialization, 380 please check FSP output HOB via U-Boot command 'fsp hob' to see 381 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 382 If such GUID does not exist, MRC cache is not avaiable on such 383 platform (eg: Intel Queensbay), which means selecting this option 384 here does not make any difference. 385 386config HAVE_MRC 387 bool "Add a System Agent binary" 388 depends on !HAVE_FSP 389 help 390 Select this option to add a System Agent binary to 391 the resulting U-Boot image. MRC stands for Memory Reference Code. 392 It is a binary blob which U-Boot uses to set up SDRAM. 393 394 Note: Without this binary U-Boot will not be able to set up its 395 SDRAM so will not boot. 396 397config CACHE_MRC_BIN 398 bool 399 depends on HAVE_MRC 400 default n 401 help 402 Enable caching for the memory reference code binary. This uses an 403 MTRR (memory type range register) to turn on caching for the section 404 of SPI flash that contains the memory reference code. This makes 405 SDRAM init run faster. 406 407config CACHE_MRC_SIZE_KB 408 int 409 depends on HAVE_MRC 410 default 512 411 help 412 Sets the size of the cached area for the memory reference code. 413 This ends at the end of SPI flash (address 0xffffffff) and is 414 measured in KB. Typically this is set to 512, providing for 0.5MB 415 of cached space. 416 417config DCACHE_RAM_BASE 418 hex 419 depends on HAVE_MRC 420 help 421 Sets the base of the data cache area in memory space. This is the 422 start address of the cache-as-RAM (CAR) area and the address varies 423 depending on the CPU. Once CAR is set up, read/write memory becomes 424 available at this address and can be used temporarily until SDRAM 425 is working. 426 427config DCACHE_RAM_SIZE 428 hex 429 depends on HAVE_MRC 430 default 0x40000 431 help 432 Sets the total size of the data cache area in memory space. This 433 sets the size of the cache-as-RAM (CAR) area. Note that much of the 434 CAR space is required by the MRC. The CAR space available to U-Boot 435 is normally at the start and typically extends to 1/4 or 1/2 of the 436 available size. 437 438config DCACHE_RAM_MRC_VAR_SIZE 439 hex 440 depends on HAVE_MRC 441 help 442 This is the amount of CAR (Cache as RAM) reserved for use by the 443 memory reference code. This depends on the implementation of the 444 memory reference code and must be set correctly or the board will 445 not boot. 446 447config HAVE_REFCODE 448 bool "Add a Reference Code binary" 449 help 450 Select this option to add a Reference Code binary to the resulting 451 U-Boot image. This is an Intel binary blob that handles system 452 initialisation, in this case the PCH and System Agent. 453 454 Note: Without this binary (on platforms that need it such as 455 broadwell) U-Boot will be missing some critical setup steps. 456 Various peripherals may fail to work. 457 458config SMP 459 bool "Enable Symmetric Multiprocessing" 460 default n 461 help 462 Enable use of more than one CPU in U-Boot and the Operating System 463 when loaded. Each CPU will be started up and information can be 464 obtained using the 'cpu' command. If this option is disabled, then 465 only one CPU will be enabled regardless of the number of CPUs 466 available. 467 468config MAX_CPUS 469 int "Maximum number of CPUs permitted" 470 depends on SMP 471 default 4 472 help 473 When using multi-CPU chips it is possible for U-Boot to start up 474 more than one CPU. The stack memory used by all of these CPUs is 475 pre-allocated so at present U-Boot wants to know the maximum 476 number of CPUs that may be present. Set this to at least as high 477 as the number of CPUs in your system (it uses about 4KB of RAM for 478 each CPU). 479 480config AP_STACK_SIZE 481 hex 482 depends on SMP 483 default 0x1000 484 help 485 Each additional CPU started by U-Boot requires its own stack. This 486 option sets the stack size used by each CPU and directly affects 487 the memory used by this initialisation process. Typically 4KB is 488 enough space. 489 490config HAVE_VGA_BIOS 491 bool "Add a VGA BIOS image" 492 help 493 Select this option if you have a VGA BIOS image that you would 494 like to add to your ROM. 495 496config VGA_BIOS_FILE 497 string "VGA BIOS image filename" 498 depends on HAVE_VGA_BIOS 499 default "vga.bin" 500 help 501 The filename of the VGA BIOS image in the board directory. 502 503config VGA_BIOS_ADDR 504 hex "VGA BIOS image location" 505 depends on HAVE_VGA_BIOS 506 default 0xfff90000 507 help 508 The location of VGA BIOS image in the SPI flash. For example, base 509 address of 0xfff90000 indicates that the image will be put at offset 510 0x90000 from the beginning of a 1MB flash device. 511 512menu "System tables" 513 depends on !EFI && !SYS_COREBOOT 514 515config GENERATE_PIRQ_TABLE 516 bool "Generate a PIRQ table" 517 default n 518 help 519 Generate a PIRQ routing table for this board. The PIRQ routing table 520 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 521 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 522 It specifies the interrupt router information as well how all the PCI 523 devices' interrupt pins are wired to PIRQs. 524 525config GENERATE_SFI_TABLE 526 bool "Generate a SFI (Simple Firmware Interface) table" 527 help 528 The Simple Firmware Interface (SFI) provides a lightweight method 529 for platform firmware to pass information to the operating system 530 via static tables in memory. Kernel SFI support is required to 531 boot on SFI-only platforms. If you have ACPI tables then these are 532 used instead. 533 534 U-Boot writes this table in write_sfi_table() just before booting 535 the OS. 536 537 For more information, see http://simplefirmware.org 538 539config GENERATE_MP_TABLE 540 bool "Generate an MP (Multi-Processor) table" 541 default n 542 help 543 Generate an MP (Multi-Processor) table for this board. The MP table 544 provides a way for the operating system to support for symmetric 545 multiprocessing as well as symmetric I/O interrupt handling with 546 the local APIC and I/O APIC. 547 548config GENERATE_ACPI_TABLE 549 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 550 default n 551 select QFW if QEMU 552 help 553 The Advanced Configuration and Power Interface (ACPI) specification 554 provides an open standard for device configuration and management 555 by the operating system. It defines platform-independent interfaces 556 for configuration and power management monitoring. 557 558endmenu 559 560config MAX_PIRQ_LINKS 561 int 562 default 8 563 help 564 This variable specifies the number of PIRQ interrupt links which are 565 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 566 Some newer chipsets offer more than four links, commonly up to PIRQH. 567 568config IRQ_SLOT_COUNT 569 int 570 default 128 571 help 572 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 573 which in turns forms a table of exact 4KiB. The default value 128 574 should be enough for most boards. If this does not fit your board, 575 change it according to your needs. 576 577config PCIE_ECAM_BASE 578 hex 579 default 0xe0000000 580 help 581 This is the memory-mapped address of PCI configuration space, which 582 is only available through the Enhanced Configuration Access 583 Mechanism (ECAM) with PCI Express. It can be set up almost 584 anywhere. Before it is set up, it is possible to access PCI 585 configuration space through I/O access, but memory access is more 586 convenient. Using this, PCI can be scanned and configured. This 587 should be set to a region that does not conflict with memory 588 assigned to PCI devices - i.e. the memory and prefetch regions, as 589 passed to pci_set_region(). 590 591config PCIE_ECAM_SIZE 592 hex 593 default 0x10000000 594 help 595 This is the size of memory-mapped address of PCI configuration space, 596 which is only available through the Enhanced Configuration Access 597 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 598 so a default 0x10000000 size covers all of the 256 buses which is the 599 maximum number of PCI buses as defined by the PCI specification. 600 601config I8259_PIC 602 bool 603 default y 604 help 605 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 606 slave) interrupt controllers. Include this to have U-Boot set up 607 the interrupt correctly. 608 609config I8254_TIMER 610 bool 611 default y 612 help 613 Intel 8254 timer contains three counters which have fixed uses. 614 Include this to have U-Boot set up the timer correctly. 615 616config SEABIOS 617 bool "Support booting SeaBIOS" 618 help 619 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 620 It can run in an emulator or natively on X86 hardware with the use 621 of coreboot/U-Boot. By turning on this option, U-Boot prepares 622 all the configuration tables that are necessary to boot SeaBIOS. 623 624 Check http://www.seabios.org/SeaBIOS for details. 625 626config HIGH_TABLE_SIZE 627 hex "Size of configuration tables which reside in high memory" 628 default 0x10000 629 depends on SEABIOS 630 help 631 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 632 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 633 puts a copy of configuration tables in high memory region which 634 is reserved on the stack before relocation. The region size is 635 determined by this option. 636 637 Increse it if the default size does not fit the board's needs. 638 This is most likely due to a large ACPI DSDT table is used. 639 640source "arch/x86/lib/efi/Kconfig" 641 642endmenu 643