1 #ifndef _ASM_CPU_SH7780_H_ 2 #define _ASM_CPU_SH7780_H_ 3 4 /* 5 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #define CACHE_OC_NUM_WAYS 1 26 #define CCR_CACHE_INIT 0x0000090b 27 28 /* Exceptions */ 29 #define TRA 0xFF000020 30 #define EXPEVT 0xFF000024 31 #define INTEVT 0xFF000028 32 33 /* Memory Management Unit */ 34 #define PTEH 0xFF000000 35 #define PTEL 0xFF000004 36 #define TTB 0xFF000008 37 #define TEA 0xFF00000C 38 #define MMUCR 0xFF000010 39 #define PASCR 0xFF000070 40 #define IRMCR 0xFF000078 41 42 /* Cache Controller */ 43 #define CCR 0xFF00001C 44 #define QACR0 0xFF000038 45 #define QACR1 0xFF00003C 46 #define RAMCR 0xFF000074 47 48 /* L Memory */ 49 #define RAMCR 0xFF000074 50 #define LSA0 0xFF000050 51 #define LSA1 0xFF000054 52 #define LDA0 0xFF000058 53 #define LDA1 0xFF00005C 54 55 /* Interrupt Controller */ 56 #define ICR0 0xFFD00000 57 #define ICR1 0xFFD0001C 58 #define INTPRI 0xFFD00010 59 #define INTREQ 0xFFD00024 60 #define INTMSK0 0xFFD00044 61 #define INTMSK1 0xFFD00048 62 #define INTMSK2 0xFFD40080 63 #define INTMSKCLR0 0xFFD00064 64 #define INTMSKCLR1 0xFFD00068 65 #define INTMSKCLR2 0xFFD40084 66 #define NMIFCR 0xFFD000C0 67 #define USERIMASK 0xFFD30000 68 #define INT2PRI0 0xFFD40000 69 #define INT2PRI1 0xFFD40004 70 #define INT2PRI2 0xFFD40008 71 #define INT2PRI3 0xFFD4000C 72 #define INT2PRI4 0xFFD40010 73 #define INT2PRI5 0xFFD40014 74 #define INT2PRI6 0xFFD40018 75 #define INT2PRI7 0xFFD4001C 76 #define INT2A0 0xFFD40030 77 #define INT2A1 0xFFD40034 78 #define INT2MSKR 0xFFD40038 79 #define INT2MSKCR 0xFFD4003C 80 #define INT2B0 0xFFD40040 81 #define INT2B1 0xFFD40044 82 #define INT2B2 0xFFD40048 83 #define INT2B3 0xFFD4004C 84 #define INT2B4 0xFFD40050 85 #define INT2B5 0xFFD40054 86 #define INT2B6 0xFFD40058 87 #define INT2B7 0xFFD4005C 88 #define INT2GPIC 0xFFD40090 89 90 /* local Bus State Controller */ 91 #define MMSELR 0xFF400020 92 #define BCR 0xFF801000 93 #define CS0BCR 0xFF802000 94 #define CS1BCR 0xFF802010 95 #define CS2BCR 0xFF802020 96 #define CS4BCR 0xFF802040 97 #define CS5BCR 0xFF802050 98 #define CS6BCR 0xFF802060 99 #define CS0WCR 0xFF802008 100 #define CS1WCR 0xFF802018 101 #define CS2WCR 0xFF802028 102 #define CS4WCR 0xFF802048 103 #define CS5WCR 0xFF802058 104 #define CS6WCR 0xFF802068 105 #define CS5PCR 0xFF802070 106 #define CS6PCR 0xFF802080 107 108 /* DDR-SDRAM I/F */ 109 #define MIM_1 0xFE800008 110 #define MIM_2 0xFE80000C 111 #define SCR_1 0xFE800010 112 #define SCR_2 0xFE800014 113 #define STR_1 0xFE800018 114 #define STR_2 0xFE80001C 115 #define SDR_1 0xFE800030 116 #define SDR_2 0xFE800034 117 #define DBK_1 0xFE800400 118 #define DBK_2 0xFE800404 119 120 /* PCI Controller */ 121 #define SH7780_PCIECR 0xFE000008 122 #define SH7780_PCIVID 0xFE040000 123 #define SH7780_PCIDID 0xFE040002 124 #define SH7780_PCICMD 0xFE040004 125 #define SH7780_PCISTATUS 0xFE040006 126 #define SH7780_PCIRID 0xFE040008 127 #define SH7780_PCIPIF 0xFE040009 128 #define SH7780_PCISUB 0xFE04000A 129 #define SH7780_PCIBCC 0xFE04000B 130 #define SH7780_PCICLS 0xFE04000C 131 #define SH7780_PCILTM 0xFE04000D 132 #define SH7780_PCIHDR 0xFE04000E 133 #define SH7780_PCIBIST 0xFE04000F 134 #define SH7780_PCIIBAR 0xFE040010 135 #define SH7780_PCIMBAR0 0xFE040014 136 #define SH7780_PCIMBAR1 0xFE040018 137 #define SH7780_PCISVID 0xFE04002C 138 #define SH7780_PCISID 0xFE04002E 139 #define SH7780_PCICP 0xFE040034 140 #define SH7780_PCIINTLINE 0xFE04003C 141 #define SH7780_PCIINTPIN 0xFE04003D 142 #define SH7780_PCIMINGNT 0xFE04003E 143 #define SH7780_PCIMAXLAT 0xFE04003F 144 #define SH7780_PCICID 0xFE040040 145 #define SH7780_PCINIP 0xFE040041 146 #define SH7780_PCIPMC 0xFE040042 147 #define SH7780_PCIPMCSR 0xFE040044 148 #define SH7780_PCIPMCSRBSE 0xFE040046 149 #define SH7780_PCI_CDD 0xFE040047 150 #define SH7780_PCICR 0xFE040100 151 #define SH7780_PCILSR0 0xFE040104 152 #define SH7780_PCILSR1 0xFE040108 153 #define SH7780_PCILAR0 0xFE04010C 154 #define SH7780_PCILAR1 0xFE040110 155 #define SH7780_PCIIR 0xFE040114 156 #define SH7780_PCIIMR 0xFE040118 157 #define SH7780_PCIAIR 0xFE04011C 158 #define SH7780_PCICIR 0xFE040120 159 #define SH7780_PCIAINT 0xFE040130 160 #define SH7780_PCIAINTM 0xFE040134 161 #define SH7780_PCIBMIR 0xFE040138 162 #define SH7780_PCIPAR 0xFE0401C0 163 #define SH7780_PCIPINT 0xFE0401CC 164 #define SH7780_PCIPINTM 0xFE0401D0 165 #define SH7780_PCIMBR0 0xFE0401E0 166 #define SH7780_PCIMBMR0 0xFE0401E4 167 #define SH7780_PCIMBR1 0xFE0401E8 168 #define SH7780_PCIMBMR1 0xFE0401EC 169 #define SH7780_PCIMBR2 0xFE0401F0 170 #define SH7780_PCIMBMR2 0xFE0401F4 171 #define SH7780_PCIIOBR 0xFE0401F8 172 #define SH7780_PCIIOBMR 0xFE0401FC 173 #define SH7780_PCICSCR0 0xFE040210 174 #define SH7780_PCICSCR1 0xFE040214 175 #define SH7780_PCICSAR0 0xFE040218 176 #define SH7780_PCICSAR1 0xFE04021C 177 #define SH7780_PCIPDR 0xFE040220 178 179 /* DMAC */ 180 #define DMAC_SAR0 0xFC808020 181 #define DMAC_DAR0 0xFC808024 182 #define DMAC_TCR0 0xFC808028 183 #define DMAC_CHCR0 0xFC80802C 184 #define DMAC_SAR1 0xFC808030 185 #define DMAC_DAR1 0xFC808034 186 #define DMAC_TCR1 0xFC808038 187 #define DMAC_CHCR1 0xFC80803C 188 #define DMAC_SAR2 0xFC808040 189 #define DMAC_DAR2 0xFC808044 190 #define DMAC_TCR2 0xFC808048 191 #define DMAC_CHCR2 0xFC80804C 192 #define DMAC_SAR3 0xFC808050 193 #define DMAC_DAR3 0xFC808054 194 #define DMAC_TCR3 0xFC808058 195 #define DMAC_CHCR3 0xFC80805C 196 #define DMAC_DMAOR0 0xFC808060 197 #define DMAC_SAR4 0xFC808070 198 #define DMAC_DAR4 0xFC808074 199 #define DMAC_TCR4 0xFC808078 200 #define DMAC_CHCR4 0xFC80807C 201 #define DMAC_SAR5 0xFC808080 202 #define DMAC_DAR5 0xFC808084 203 #define DMAC_TCR5 0xFC808088 204 #define DMAC_CHCR5 0xFC80808C 205 #define DMAC_SARB0 0xFC808120 206 #define DMAC_DARB0 0xFC808124 207 #define DMAC_TCRB0 0xFC808128 208 #define DMAC_SARB1 0xFC808130 209 #define DMAC_DARB1 0xFC808134 210 #define DMAC_TCRB1 0xFC808138 211 #define DMAC_SARB2 0xFC808140 212 #define DMAC_DARB2 0xFC808144 213 #define DMAC_TCRB2 0xFC808148 214 #define DMAC_SARB3 0xFC808150 215 #define DMAC_DARB3 0xFC808154 216 #define DMAC_TCRB3 0xFC808158 217 #define DMAC_DMARS0 0xFC809000 218 #define DMAC_DMARS1 0xFC809004 219 #define DMAC_DMARS2 0xFC809008 220 #define DMAC_SAR6 0xFC818020 221 #define DMAC_DAR6 0xFC818024 222 #define DMAC_TCR6 0xFC818028 223 #define DMAC_CHCR6 0xFC81802C 224 #define DMAC_SAR7 0xFC818030 225 #define DMAC_DAR7 0xFC818034 226 #define DMAC_TCR7 0xFC818038 227 #define DMAC_CHCR7 0xFC81803C 228 #define DMAC_SAR8 0xFC818040 229 #define DMAC_DAR8 0xFC818044 230 #define DMAC_TCR8 0xFC818048 231 #define DMAC_CHCR8 0xFC81804C 232 #define DMAC_SAR9 0xFC818050 233 #define DMAC_DAR9 0xFC818054 234 #define DMAC_TCR9 0xFC818058 235 #define DMAC_CHCR9 0xFC81805C 236 #define DMAC_DMAOR1 0xFC818060 237 #define DMAC_SAR10 0xFC818070 238 #define DMAC_DAR10 0xFC818074 239 #define DMAC_TCR10 0xFC818078 240 #define DMAC_CHCR10 0xFC81807C 241 #define DMAC_SAR11 0xFC818080 242 #define DMAC_DAR11 0xFC818084 243 #define DMAC_TCR11 0xFC818088 244 #define DMAC_CHCR11 0xFC81808C 245 #define DMAC_SARB6 0xFC818120 246 #define DMAC_DARB6 0xFC818124 247 #define DMAC_TCRB6 0xFC818128 248 #define DMAC_SARB7 0xFC818130 249 #define DMAC_DARB7 0xFC818134 250 #define DMAC_TCRB7 0xFC818138 251 #define DMAC_SARB8 0xFC818140 252 #define DMAC_DARB8 0xFC818144 253 #define DMAC_TCRB8 0xFC818148 254 #define DMAC_SARB9 0xFC818150 255 #define DMAC_DARB9 0xFC818154 256 #define DMAC_TCRB9 0xFC818158 257 258 /* Clock Pulse Generator */ 259 #define FRQCR 0xFFC80000 260 #define PLLCR 0xFFC80024 261 #define MSTPCR 0xFFC80030 262 263 /* Watchdog Timer and Reset */ 264 #define WTCNT WDTCNT 265 #define WDTST 0xFFCC0000 266 #define WDTCSR 0xFFCC0004 267 #define WDTBST 0xFFCC0008 268 #define WDTCNT 0xFFCC0010 269 #define WDTBCNT 0xFFCC0018 270 271 /* System Control */ 272 #define MSTPCR 0xFFC80030 273 274 /* Timer Unit */ 275 #define TSTR TSTR0 276 #define TOCR 0xFFD80000 277 #define TSTR0 0xFFD80004 278 #define TCOR0 0xFFD80008 279 #define TCNT0 0xFFD8000C 280 #define TCR0 0xFFD80010 281 #define TCOR1 0xFFD80014 282 #define TCNT1 0xFFD80018 283 #define TCR1 0xFFD8001C 284 #define TCOR2 0xFFD80020 285 #define TCNT2 0xFFD80024 286 #define TCR2 0xFFD80028 287 #define TCPR2 0xFFD8002C 288 #define TSTR1 0xFFDC0004 289 #define TCOR3 0xFFDC0008 290 #define TCNT3 0xFFDC000C 291 #define TCR3 0xFFDC0010 292 #define TCOR4 0xFFDC0014 293 #define TCNT4 0xFFDC0018 294 #define TCR4 0xFFDC001C 295 #define TCOR5 0xFFDC0020 296 #define TCNT5 0xFFDC0024 297 #define TCR5 0xFFDC0028 298 299 /* Timer/Counter */ 300 #define CMTCFG 0xFFE30000 301 #define CMTFRT 0xFFE30004 302 #define CMTCTL 0xFFE30008 303 #define CMTIRQS 0xFFE3000C 304 #define CMTCH0T 0xFFE30010 305 #define CMTCH0ST 0xFFE30020 306 #define CMTCH0C 0xFFE30030 307 #define CMTCH1T 0xFFE30014 308 #define CMTCH1ST 0xFFE30024 309 #define CMTCH1C 0xFFE30034 310 #define CMTCH2T 0xFFE30018 311 #define CMTCH2C 0xFFE30038 312 #define CMTCH3T 0xFFE3001C 313 #define CMTCH3C 0xFFE3003C 314 315 /* Realtime Clock */ 316 #define R64CNT 0xFFE80000 317 #define RSECCNT 0xFFE80004 318 #define RMINCNT 0xFFE80008 319 #define RHRCNT 0xFFE8000C 320 #define RWKCNT 0xFFE80010 321 #define RDAYCNT 0xFFE80014 322 #define RMONCNT 0xFFE80018 323 #define RYRCNT 0xFFE8001C 324 #define RSECAR 0xFFE80020 325 #define RMINAR 0xFFE80024 326 #define RHRAR 0xFFE80028 327 #define RWKAR 0xFFE8002C 328 #define RDAYAR 0xFFE80030 329 #define RMONAR 0xFFE80034 330 #define RCR1 0xFFE80038 331 #define RCR2 0xFFE8003C 332 #define RCR3 0xFFE80050 333 #define RYRAR 0xFFE80054 334 335 /* Serial Communication Interface with FIFO */ 336 #define SCSMR0 0xFFE00000 337 #define SCIF0_BASE SCSMR0 338 339 /* Serial I/O with FIFO */ 340 #define SIMDR 0xFFE20000 341 #define SISCR 0xFFE20002 342 #define SITDAR 0xFFE20004 343 #define SIRDAR 0xFFE20006 344 #define SICDAR 0xFFE20008 345 #define SICTR 0xFFE2000C 346 #define SIFCTR 0xFFE20010 347 #define SISTR 0xFFE20014 348 #define SIIER 0xFFE20016 349 #define SITCR 0xFFE20028 350 #define SIRCR 0xFFE2002C 351 #define SPICR 0xFFE20030 352 353 /* Serial Protocol Interface */ 354 #define SPCR 0xFFE50000 355 #define SPSR 0xFFE50004 356 #define SPSCR 0xFFE50008 357 #define SPTBR 0xFFE5000C 358 #define SPRBR 0xFFE50010 359 360 /* Multimedia Card Interface */ 361 #define CMDR0 0xFFE60000 362 #define CMDR1 0xFFE60001 363 #define CMDR2 0xFFE60002 364 #define CMDR3 0xFFE60003 365 #define CMDR4 0xFFE60004 366 #define CMDR5 0xFFE60005 367 #define CMDSTRT 0xFFE60006 368 #define OPCR 0xFFE6000A 369 #define CSTR 0xFFE6000B 370 #define INTCR0 0xFFE6000C 371 #define INTCR1 0xFFE6000D 372 #define INTSTR0 0xFFE6000E 373 #define INTSTR1 0xFFE6000F 374 #define CLKON 0xFFE60010 375 #define CTOCR 0xFFE60011 376 #define TBCR 0xFFE60014 377 #define MODER 0xFFE60016 378 #define CMDTYR 0xFFE60018 379 #define RSPTYR 0xFFE60019 380 #define TBNCR 0xFFE6001A 381 #define RSPR0 0xFFE60020 382 #define RSPR1 0xFFE60021 383 #define RSPR2 0xFFE60022 384 #define RSPR3 0xFFE60023 385 #define RSPR4 0xFFE60024 386 #define RSPR5 0xFFE60025 387 #define RSPR6 0xFFE60026 388 #define RSPR7 0xFFE60027 389 #define RSPR8 0xFFE60028 390 #define RSPR9 0xFFE60029 391 #define RSPR10 0xFFE6002A 392 #define RSPR11 0xFFE6002B 393 #define RSPR12 0xFFE6002C 394 #define RSPR13 0xFFE6002D 395 #define RSPR14 0xFFE6002E 396 #define RSPR15 0xFFE6002F 397 #define RSPR16 0xFFE60030 398 #define RSPRD 0xFFE60031 399 #define DTOUTR 0xFFE60032 400 #define DR 0xFFE60040 401 #define DMACR 0xFFE60044 402 #define INTCR2 0xFFE60046 403 #define INTSTR2 0xFFE60048 404 405 /* Audio Codec Interface */ 406 #define HACCR 0xFFE40008 407 #define HACCSAR 0xFFE40020 408 #define HACCSDR 0xFFE40024 409 #define HACPCML 0xFFE40028 410 #define HACPCMR 0xFFE4002C 411 #define HACTIER 0xFFE40050 412 #define HACTSR 0xFFE40054 413 #define HACRIER 0xFFE40058 414 #define HACRSR 0xFFE4005C 415 #define HACACR 0xFFE40060 416 417 /* Serial Sound Interface */ 418 #define SSICR 0xFFE70000 419 #define SSISR 0xFFE70004 420 #define SSITDR 0xFFE70008 421 #define SSIRDR 0xFFE7000C 422 423 /* Flash memory Controller */ 424 #define FLCMNCR 0xFFE90000 425 #define FLCMDCR 0xFFE90004 426 #define FLCMCDR 0xFFE90008 427 #define FLADR 0xFFE9000C 428 #define FLDATAR 0xFFE90010 429 #define FLDTCNTR 0xFFE90014 430 #define FLINTDMACR 0xFFE90018 431 #define FLBSYTMR 0xFFE9001C 432 #define FLBSYCNT 0xFFE90020 433 #define FLTRCR 0xFFE9002C 434 435 /* General Purpose I/O */ 436 #define PACR 0xFFEA0000 437 #define PBCR 0xFFEA0002 438 #define PCCR 0xFFEA0004 439 #define PDCR 0xFFEA0006 440 #define PECR 0xFFEA0008 441 #define PFCR 0xFFEA000A 442 #define PGCR 0xFFEA000C 443 #define PHCR 0xFFEA000E 444 #define PJCR 0xFFEA0010 445 #define PKCR 0xFFEA0012 446 #define PLCR 0xFFEA0014 447 #define PMCR 0xFFEA0016 448 #define PADR 0xFFEA0020 449 #define PBDR 0xFFEA0022 450 #define PCDR 0xFFEA0024 451 #define PDDR 0xFFEA0026 452 #define PEDR 0xFFEA0028 453 #define PFDR 0xFFEA002A 454 #define PGDR 0xFFEA002C 455 #define PHDR 0xFFEA002E 456 #define PJDR 0xFFEA0030 457 #define PKDR 0xFFEA0032 458 #define PLDR 0xFFEA0034 459 #define PMDR 0xFFEA0036 460 #define PEPUPR 0xFFEA0048 461 #define PHPUPR 0xFFEA004E 462 #define PJPUPR 0xFFEA0050 463 #define PKPUPR 0xFFEA0052 464 #define PMPUPR 0xFFEA0056 465 #define PPUPR1 0xFFEA0060 466 #define PPUPR2 0xFFEA0062 467 #define PMSELR 0xFFEA0080 468 469 /* User Break Controller */ 470 #define CBR0 0xFF200000 471 #define CRR0 0xFF200004 472 #define CAR0 0xFF200008 473 #define CAMR0 0xFF20000C 474 #define CBR1 0xFF200020 475 #define CRR1 0xFF200024 476 #define CAR1 0xFF200028 477 #define CAMR1 0xFF20002C 478 #define CDR1 0xFF200030 479 #define CDMR1 0xFF200034 480 #define CETR1 0xFF200038 481 #define CCMFR 0xFF200600 482 #define CBCR 0xFF200620 483 484 #endif /* _ASM_CPU_SH7780_H_ */ 485