1*819833afSPeter Tyser #ifndef _ASM_CPU_SH7780_H_ 2*819833afSPeter Tyser #define _ASM_CPU_SH7780_H_ 3*819833afSPeter Tyser 4*819833afSPeter Tyser /* 5*819833afSPeter Tyser * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 6*819833afSPeter Tyser * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> 7*819833afSPeter Tyser * 8*819833afSPeter Tyser * This program is free software; you can redistribute it and/or 9*819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 10*819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 11*819833afSPeter Tyser * the License, or (at your option) any later version. 12*819833afSPeter Tyser * 13*819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 14*819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*819833afSPeter Tyser * GNU General Public License for more details. 17*819833afSPeter Tyser * 18*819833afSPeter Tyser * You should have received a copy of the GNU General Public License 19*819833afSPeter Tyser * along with this program; if not, write to the Free Software 20*819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*819833afSPeter Tyser * MA 02111-1307 USA 22*819833afSPeter Tyser * 23*819833afSPeter Tyser */ 24*819833afSPeter Tyser 25*819833afSPeter Tyser #define CACHE_OC_NUM_WAYS 1 26*819833afSPeter Tyser #define CCR_CACHE_INIT 0x0000090b 27*819833afSPeter Tyser 28*819833afSPeter Tyser /* Exceptions */ 29*819833afSPeter Tyser #define TRA 0xFF000020 30*819833afSPeter Tyser #define EXPEVT 0xFF000024 31*819833afSPeter Tyser #define INTEVT 0xFF000028 32*819833afSPeter Tyser 33*819833afSPeter Tyser /* Memory Management Unit */ 34*819833afSPeter Tyser #define PTEH 0xFF000000 35*819833afSPeter Tyser #define PTEL 0xFF000004 36*819833afSPeter Tyser #define TTB 0xFF000008 37*819833afSPeter Tyser #define TEA 0xFF00000C 38*819833afSPeter Tyser #define MMUCR 0xFF000010 39*819833afSPeter Tyser #define PASCR 0xFF000070 40*819833afSPeter Tyser #define IRMCR 0xFF000078 41*819833afSPeter Tyser 42*819833afSPeter Tyser /* Cache Controller */ 43*819833afSPeter Tyser #define CCR 0xFF00001C 44*819833afSPeter Tyser #define QACR0 0xFF000038 45*819833afSPeter Tyser #define QACR1 0xFF00003C 46*819833afSPeter Tyser #define RAMCR 0xFF000074 47*819833afSPeter Tyser 48*819833afSPeter Tyser /* L Memory */ 49*819833afSPeter Tyser #define RAMCR 0xFF000074 50*819833afSPeter Tyser #define LSA0 0xFF000050 51*819833afSPeter Tyser #define LSA1 0xFF000054 52*819833afSPeter Tyser #define LDA0 0xFF000058 53*819833afSPeter Tyser #define LDA1 0xFF00005C 54*819833afSPeter Tyser 55*819833afSPeter Tyser /* Interrupt Controller */ 56*819833afSPeter Tyser #define ICR0 0xFFD00000 57*819833afSPeter Tyser #define ICR1 0xFFD0001C 58*819833afSPeter Tyser #define INTPRI 0xFFD00010 59*819833afSPeter Tyser #define INTREQ 0xFFD00024 60*819833afSPeter Tyser #define INTMSK0 0xFFD00044 61*819833afSPeter Tyser #define INTMSK1 0xFFD00048 62*819833afSPeter Tyser #define INTMSK2 0xFFD40080 63*819833afSPeter Tyser #define INTMSKCLR0 0xFFD00064 64*819833afSPeter Tyser #define INTMSKCLR1 0xFFD00068 65*819833afSPeter Tyser #define INTMSKCLR2 0xFFD40084 66*819833afSPeter Tyser #define NMIFCR 0xFFD000C0 67*819833afSPeter Tyser #define USERIMASK 0xFFD30000 68*819833afSPeter Tyser #define INT2PRI0 0xFFD40000 69*819833afSPeter Tyser #define INT2PRI1 0xFFD40004 70*819833afSPeter Tyser #define INT2PRI2 0xFFD40008 71*819833afSPeter Tyser #define INT2PRI3 0xFFD4000C 72*819833afSPeter Tyser #define INT2PRI4 0xFFD40010 73*819833afSPeter Tyser #define INT2PRI5 0xFFD40014 74*819833afSPeter Tyser #define INT2PRI6 0xFFD40018 75*819833afSPeter Tyser #define INT2PRI7 0xFFD4001C 76*819833afSPeter Tyser #define INT2A0 0xFFD40030 77*819833afSPeter Tyser #define INT2A1 0xFFD40034 78*819833afSPeter Tyser #define INT2MSKR 0xFFD40038 79*819833afSPeter Tyser #define INT2MSKCR 0xFFD4003C 80*819833afSPeter Tyser #define INT2B0 0xFFD40040 81*819833afSPeter Tyser #define INT2B1 0xFFD40044 82*819833afSPeter Tyser #define INT2B2 0xFFD40048 83*819833afSPeter Tyser #define INT2B3 0xFFD4004C 84*819833afSPeter Tyser #define INT2B4 0xFFD40050 85*819833afSPeter Tyser #define INT2B5 0xFFD40054 86*819833afSPeter Tyser #define INT2B6 0xFFD40058 87*819833afSPeter Tyser #define INT2B7 0xFFD4005C 88*819833afSPeter Tyser #define INT2GPIC 0xFFD40090 89*819833afSPeter Tyser 90*819833afSPeter Tyser /* local Bus State Controller */ 91*819833afSPeter Tyser #define MMSELR 0xFF400020 92*819833afSPeter Tyser #define BCR 0xFF801000 93*819833afSPeter Tyser #define CS0BCR 0xFF802000 94*819833afSPeter Tyser #define CS1BCR 0xFF802010 95*819833afSPeter Tyser #define CS2BCR 0xFF802020 96*819833afSPeter Tyser #define CS4BCR 0xFF802040 97*819833afSPeter Tyser #define CS5BCR 0xFF802050 98*819833afSPeter Tyser #define CS6BCR 0xFF802060 99*819833afSPeter Tyser #define CS0WCR 0xFF802008 100*819833afSPeter Tyser #define CS1WCR 0xFF802018 101*819833afSPeter Tyser #define CS2WCR 0xFF802028 102*819833afSPeter Tyser #define CS4WCR 0xFF802048 103*819833afSPeter Tyser #define CS5WCR 0xFF802058 104*819833afSPeter Tyser #define CS6WCR 0xFF802068 105*819833afSPeter Tyser #define CS5PCR 0xFF802070 106*819833afSPeter Tyser #define CS6PCR 0xFF802080 107*819833afSPeter Tyser 108*819833afSPeter Tyser /* DDR-SDRAM I/F */ 109*819833afSPeter Tyser #define MIM_1 0xFE800008 110*819833afSPeter Tyser #define MIM_2 0xFE80000C 111*819833afSPeter Tyser #define SCR_1 0xFE800010 112*819833afSPeter Tyser #define SCR_2 0xFE800014 113*819833afSPeter Tyser #define STR_1 0xFE800018 114*819833afSPeter Tyser #define STR_2 0xFE80001C 115*819833afSPeter Tyser #define SDR_1 0xFE800030 116*819833afSPeter Tyser #define SDR_2 0xFE800034 117*819833afSPeter Tyser #define DBK_1 0xFE800400 118*819833afSPeter Tyser #define DBK_2 0xFE800404 119*819833afSPeter Tyser 120*819833afSPeter Tyser /* PCI Controller */ 121*819833afSPeter Tyser #define SH7780_PCIECR 0xFE000008 122*819833afSPeter Tyser #define SH7780_PCIVID 0xFE040000 123*819833afSPeter Tyser #define SH7780_PCIDID 0xFE040002 124*819833afSPeter Tyser #define SH7780_PCICMD 0xFE040004 125*819833afSPeter Tyser #define SH7780_PCISTATUS 0xFE040006 126*819833afSPeter Tyser #define SH7780_PCIRID 0xFE040008 127*819833afSPeter Tyser #define SH7780_PCIPIF 0xFE040009 128*819833afSPeter Tyser #define SH7780_PCISUB 0xFE04000A 129*819833afSPeter Tyser #define SH7780_PCIBCC 0xFE04000B 130*819833afSPeter Tyser #define SH7780_PCICLS 0xFE04000C 131*819833afSPeter Tyser #define SH7780_PCILTM 0xFE04000D 132*819833afSPeter Tyser #define SH7780_PCIHDR 0xFE04000E 133*819833afSPeter Tyser #define SH7780_PCIBIST 0xFE04000F 134*819833afSPeter Tyser #define SH7780_PCIIBAR 0xFE040010 135*819833afSPeter Tyser #define SH7780_PCIMBAR0 0xFE040014 136*819833afSPeter Tyser #define SH7780_PCIMBAR1 0xFE040018 137*819833afSPeter Tyser #define SH7780_PCISVID 0xFE04002C 138*819833afSPeter Tyser #define SH7780_PCISID 0xFE04002E 139*819833afSPeter Tyser #define SH7780_PCICP 0xFE040034 140*819833afSPeter Tyser #define SH7780_PCIINTLINE 0xFE04003C 141*819833afSPeter Tyser #define SH7780_PCIINTPIN 0xFE04003D 142*819833afSPeter Tyser #define SH7780_PCIMINGNT 0xFE04003E 143*819833afSPeter Tyser #define SH7780_PCIMAXLAT 0xFE04003F 144*819833afSPeter Tyser #define SH7780_PCICID 0xFE040040 145*819833afSPeter Tyser #define SH7780_PCINIP 0xFE040041 146*819833afSPeter Tyser #define SH7780_PCIPMC 0xFE040042 147*819833afSPeter Tyser #define SH7780_PCIPMCSR 0xFE040044 148*819833afSPeter Tyser #define SH7780_PCIPMCSRBSE 0xFE040046 149*819833afSPeter Tyser #define SH7780_PCI_CDD 0xFE040047 150*819833afSPeter Tyser #define SH7780_PCICR 0xFE040100 151*819833afSPeter Tyser #define SH7780_PCILSR0 0xFE040104 152*819833afSPeter Tyser #define SH7780_PCILSR1 0xFE040108 153*819833afSPeter Tyser #define SH7780_PCILAR0 0xFE04010C 154*819833afSPeter Tyser #define SH7780_PCILAR1 0xFE040110 155*819833afSPeter Tyser #define SH7780_PCIIR 0xFE040114 156*819833afSPeter Tyser #define SH7780_PCIIMR 0xFE040118 157*819833afSPeter Tyser #define SH7780_PCIAIR 0xFE04011C 158*819833afSPeter Tyser #define SH7780_PCICIR 0xFE040120 159*819833afSPeter Tyser #define SH7780_PCIAINT 0xFE040130 160*819833afSPeter Tyser #define SH7780_PCIAINTM 0xFE040134 161*819833afSPeter Tyser #define SH7780_PCIBMIR 0xFE040138 162*819833afSPeter Tyser #define SH7780_PCIPAR 0xFE0401C0 163*819833afSPeter Tyser #define SH7780_PCIPINT 0xFE0401CC 164*819833afSPeter Tyser #define SH7780_PCIPINTM 0xFE0401D0 165*819833afSPeter Tyser #define SH7780_PCIMBR0 0xFE0401E0 166*819833afSPeter Tyser #define SH7780_PCIMBMR0 0xFE0401E4 167*819833afSPeter Tyser #define SH7780_PCIMBR1 0xFE0401E8 168*819833afSPeter Tyser #define SH7780_PCIMBMR1 0xFE0401EC 169*819833afSPeter Tyser #define SH7780_PCIMBR2 0xFE0401F0 170*819833afSPeter Tyser #define SH7780_PCIMBMR2 0xFE0401F4 171*819833afSPeter Tyser #define SH7780_PCIIOBR 0xFE0401F8 172*819833afSPeter Tyser #define SH7780_PCIIOBMR 0xFE0401FC 173*819833afSPeter Tyser #define SH7780_PCICSCR0 0xFE040210 174*819833afSPeter Tyser #define SH7780_PCICSCR1 0xFE040214 175*819833afSPeter Tyser #define SH7780_PCICSAR0 0xFE040218 176*819833afSPeter Tyser #define SH7780_PCICSAR1 0xFE04021C 177*819833afSPeter Tyser #define SH7780_PCIPDR 0xFE040220 178*819833afSPeter Tyser 179*819833afSPeter Tyser /* DMAC */ 180*819833afSPeter Tyser #define DMAC_SAR0 0xFC808020 181*819833afSPeter Tyser #define DMAC_DAR0 0xFC808024 182*819833afSPeter Tyser #define DMAC_TCR0 0xFC808028 183*819833afSPeter Tyser #define DMAC_CHCR0 0xFC80802C 184*819833afSPeter Tyser #define DMAC_SAR1 0xFC808030 185*819833afSPeter Tyser #define DMAC_DAR1 0xFC808034 186*819833afSPeter Tyser #define DMAC_TCR1 0xFC808038 187*819833afSPeter Tyser #define DMAC_CHCR1 0xFC80803C 188*819833afSPeter Tyser #define DMAC_SAR2 0xFC808040 189*819833afSPeter Tyser #define DMAC_DAR2 0xFC808044 190*819833afSPeter Tyser #define DMAC_TCR2 0xFC808048 191*819833afSPeter Tyser #define DMAC_CHCR2 0xFC80804C 192*819833afSPeter Tyser #define DMAC_SAR3 0xFC808050 193*819833afSPeter Tyser #define DMAC_DAR3 0xFC808054 194*819833afSPeter Tyser #define DMAC_TCR3 0xFC808058 195*819833afSPeter Tyser #define DMAC_CHCR3 0xFC80805C 196*819833afSPeter Tyser #define DMAC_DMAOR0 0xFC808060 197*819833afSPeter Tyser #define DMAC_SAR4 0xFC808070 198*819833afSPeter Tyser #define DMAC_DAR4 0xFC808074 199*819833afSPeter Tyser #define DMAC_TCR4 0xFC808078 200*819833afSPeter Tyser #define DMAC_CHCR4 0xFC80807C 201*819833afSPeter Tyser #define DMAC_SAR5 0xFC808080 202*819833afSPeter Tyser #define DMAC_DAR5 0xFC808084 203*819833afSPeter Tyser #define DMAC_TCR5 0xFC808088 204*819833afSPeter Tyser #define DMAC_CHCR5 0xFC80808C 205*819833afSPeter Tyser #define DMAC_SARB0 0xFC808120 206*819833afSPeter Tyser #define DMAC_DARB0 0xFC808124 207*819833afSPeter Tyser #define DMAC_TCRB0 0xFC808128 208*819833afSPeter Tyser #define DMAC_SARB1 0xFC808130 209*819833afSPeter Tyser #define DMAC_DARB1 0xFC808134 210*819833afSPeter Tyser #define DMAC_TCRB1 0xFC808138 211*819833afSPeter Tyser #define DMAC_SARB2 0xFC808140 212*819833afSPeter Tyser #define DMAC_DARB2 0xFC808144 213*819833afSPeter Tyser #define DMAC_TCRB2 0xFC808148 214*819833afSPeter Tyser #define DMAC_SARB3 0xFC808150 215*819833afSPeter Tyser #define DMAC_DARB3 0xFC808154 216*819833afSPeter Tyser #define DMAC_TCRB3 0xFC808158 217*819833afSPeter Tyser #define DMAC_DMARS0 0xFC809000 218*819833afSPeter Tyser #define DMAC_DMARS1 0xFC809004 219*819833afSPeter Tyser #define DMAC_DMARS2 0xFC809008 220*819833afSPeter Tyser #define DMAC_SAR6 0xFC818020 221*819833afSPeter Tyser #define DMAC_DAR6 0xFC818024 222*819833afSPeter Tyser #define DMAC_TCR6 0xFC818028 223*819833afSPeter Tyser #define DMAC_CHCR6 0xFC81802C 224*819833afSPeter Tyser #define DMAC_SAR7 0xFC818030 225*819833afSPeter Tyser #define DMAC_DAR7 0xFC818034 226*819833afSPeter Tyser #define DMAC_TCR7 0xFC818038 227*819833afSPeter Tyser #define DMAC_CHCR7 0xFC81803C 228*819833afSPeter Tyser #define DMAC_SAR8 0xFC818040 229*819833afSPeter Tyser #define DMAC_DAR8 0xFC818044 230*819833afSPeter Tyser #define DMAC_TCR8 0xFC818048 231*819833afSPeter Tyser #define DMAC_CHCR8 0xFC81804C 232*819833afSPeter Tyser #define DMAC_SAR9 0xFC818050 233*819833afSPeter Tyser #define DMAC_DAR9 0xFC818054 234*819833afSPeter Tyser #define DMAC_TCR9 0xFC818058 235*819833afSPeter Tyser #define DMAC_CHCR9 0xFC81805C 236*819833afSPeter Tyser #define DMAC_DMAOR1 0xFC818060 237*819833afSPeter Tyser #define DMAC_SAR10 0xFC818070 238*819833afSPeter Tyser #define DMAC_DAR10 0xFC818074 239*819833afSPeter Tyser #define DMAC_TCR10 0xFC818078 240*819833afSPeter Tyser #define DMAC_CHCR10 0xFC81807C 241*819833afSPeter Tyser #define DMAC_SAR11 0xFC818080 242*819833afSPeter Tyser #define DMAC_DAR11 0xFC818084 243*819833afSPeter Tyser #define DMAC_TCR11 0xFC818088 244*819833afSPeter Tyser #define DMAC_CHCR11 0xFC81808C 245*819833afSPeter Tyser #define DMAC_SARB6 0xFC818120 246*819833afSPeter Tyser #define DMAC_DARB6 0xFC818124 247*819833afSPeter Tyser #define DMAC_TCRB6 0xFC818128 248*819833afSPeter Tyser #define DMAC_SARB7 0xFC818130 249*819833afSPeter Tyser #define DMAC_DARB7 0xFC818134 250*819833afSPeter Tyser #define DMAC_TCRB7 0xFC818138 251*819833afSPeter Tyser #define DMAC_SARB8 0xFC818140 252*819833afSPeter Tyser #define DMAC_DARB8 0xFC818144 253*819833afSPeter Tyser #define DMAC_TCRB8 0xFC818148 254*819833afSPeter Tyser #define DMAC_SARB9 0xFC818150 255*819833afSPeter Tyser #define DMAC_DARB9 0xFC818154 256*819833afSPeter Tyser #define DMAC_TCRB9 0xFC818158 257*819833afSPeter Tyser 258*819833afSPeter Tyser /* Clock Pulse Generator */ 259*819833afSPeter Tyser #define FRQCR 0xFFC80000 260*819833afSPeter Tyser #define PLLCR 0xFFC80024 261*819833afSPeter Tyser #define MSTPCR 0xFFC80030 262*819833afSPeter Tyser 263*819833afSPeter Tyser /* Watchdog Timer and Reset */ 264*819833afSPeter Tyser #define WTCNT WDTCNT 265*819833afSPeter Tyser #define WDTST 0xFFCC0000 266*819833afSPeter Tyser #define WDTCSR 0xFFCC0004 267*819833afSPeter Tyser #define WDTBST 0xFFCC0008 268*819833afSPeter Tyser #define WDTCNT 0xFFCC0010 269*819833afSPeter Tyser #define WDTBCNT 0xFFCC0018 270*819833afSPeter Tyser 271*819833afSPeter Tyser /* System Control */ 272*819833afSPeter Tyser #define MSTPCR 0xFFC80030 273*819833afSPeter Tyser 274*819833afSPeter Tyser /* Timer Unit */ 275*819833afSPeter Tyser #define TSTR TSTR0 276*819833afSPeter Tyser #define TOCR 0xFFD80000 277*819833afSPeter Tyser #define TSTR0 0xFFD80004 278*819833afSPeter Tyser #define TCOR0 0xFFD80008 279*819833afSPeter Tyser #define TCNT0 0xFFD8000C 280*819833afSPeter Tyser #define TCR0 0xFFD80010 281*819833afSPeter Tyser #define TCOR1 0xFFD80014 282*819833afSPeter Tyser #define TCNT1 0xFFD80018 283*819833afSPeter Tyser #define TCR1 0xFFD8001C 284*819833afSPeter Tyser #define TCOR2 0xFFD80020 285*819833afSPeter Tyser #define TCNT2 0xFFD80024 286*819833afSPeter Tyser #define TCR2 0xFFD80028 287*819833afSPeter Tyser #define TCPR2 0xFFD8002C 288*819833afSPeter Tyser #define TSTR1 0xFFDC0004 289*819833afSPeter Tyser #define TCOR3 0xFFDC0008 290*819833afSPeter Tyser #define TCNT3 0xFFDC000C 291*819833afSPeter Tyser #define TCR3 0xFFDC0010 292*819833afSPeter Tyser #define TCOR4 0xFFDC0014 293*819833afSPeter Tyser #define TCNT4 0xFFDC0018 294*819833afSPeter Tyser #define TCR4 0xFFDC001C 295*819833afSPeter Tyser #define TCOR5 0xFFDC0020 296*819833afSPeter Tyser #define TCNT5 0xFFDC0024 297*819833afSPeter Tyser #define TCR5 0xFFDC0028 298*819833afSPeter Tyser 299*819833afSPeter Tyser /* Timer/Counter */ 300*819833afSPeter Tyser #define CMTCFG 0xFFE30000 301*819833afSPeter Tyser #define CMTFRT 0xFFE30004 302*819833afSPeter Tyser #define CMTCTL 0xFFE30008 303*819833afSPeter Tyser #define CMTIRQS 0xFFE3000C 304*819833afSPeter Tyser #define CMTCH0T 0xFFE30010 305*819833afSPeter Tyser #define CMTCH0ST 0xFFE30020 306*819833afSPeter Tyser #define CMTCH0C 0xFFE30030 307*819833afSPeter Tyser #define CMTCH1T 0xFFE30014 308*819833afSPeter Tyser #define CMTCH1ST 0xFFE30024 309*819833afSPeter Tyser #define CMTCH1C 0xFFE30034 310*819833afSPeter Tyser #define CMTCH2T 0xFFE30018 311*819833afSPeter Tyser #define CMTCH2C 0xFFE30038 312*819833afSPeter Tyser #define CMTCH3T 0xFFE3001C 313*819833afSPeter Tyser #define CMTCH3C 0xFFE3003C 314*819833afSPeter Tyser 315*819833afSPeter Tyser /* Realtime Clock */ 316*819833afSPeter Tyser #define R64CNT 0xFFE80000 317*819833afSPeter Tyser #define RSECCNT 0xFFE80004 318*819833afSPeter Tyser #define RMINCNT 0xFFE80008 319*819833afSPeter Tyser #define RHRCNT 0xFFE8000C 320*819833afSPeter Tyser #define RWKCNT 0xFFE80010 321*819833afSPeter Tyser #define RDAYCNT 0xFFE80014 322*819833afSPeter Tyser #define RMONCNT 0xFFE80018 323*819833afSPeter Tyser #define RYRCNT 0xFFE8001C 324*819833afSPeter Tyser #define RSECAR 0xFFE80020 325*819833afSPeter Tyser #define RMINAR 0xFFE80024 326*819833afSPeter Tyser #define RHRAR 0xFFE80028 327*819833afSPeter Tyser #define RWKAR 0xFFE8002C 328*819833afSPeter Tyser #define RDAYAR 0xFFE80030 329*819833afSPeter Tyser #define RMONAR 0xFFE80034 330*819833afSPeter Tyser #define RCR1 0xFFE80038 331*819833afSPeter Tyser #define RCR2 0xFFE8003C 332*819833afSPeter Tyser #define RCR3 0xFFE80050 333*819833afSPeter Tyser #define RYRAR 0xFFE80054 334*819833afSPeter Tyser 335*819833afSPeter Tyser /* Serial Communication Interface with FIFO */ 336*819833afSPeter Tyser #define SCIF0_BASE SCSMR0 337*819833afSPeter Tyser #define SCSMR0 0xFFE00000 338*819833afSPeter Tyser #define SCBRR0 0xFFE00004 339*819833afSPeter Tyser #define SCSCR0 0xFFE00008 340*819833afSPeter Tyser #define SCFSR0 0xFFE00010 341*819833afSPeter Tyser #define SCFCR0 0xFFE00018 342*819833afSPeter Tyser #define SCTFDR0 0xFFE0001C 343*819833afSPeter Tyser #define SCRFDR0 0xFFE00020 344*819833afSPeter Tyser #define SCSPTR0 0xFFE00024 345*819833afSPeter Tyser #define SCLSR0 0xFFE00028 346*819833afSPeter Tyser #define SCRER0 0xFFE0002C 347*819833afSPeter Tyser #define SCSMR1 0xFFE10000 348*819833afSPeter Tyser #define SCBRR1 0xFFE10004 349*819833afSPeter Tyser #define SCSCR1 0xFFE10008 350*819833afSPeter Tyser #define SCFSR1 0xFFE10010 351*819833afSPeter Tyser #define SCFCR1 0xFFE10018 352*819833afSPeter Tyser #define SCTFDR1 0xFFE1001C 353*819833afSPeter Tyser #define SCRFDR1 0xFFE10020 354*819833afSPeter Tyser #define SCSPTR1 0xFFE10024 355*819833afSPeter Tyser #define SCLSR1 0xFFE10028 356*819833afSPeter Tyser #define SCRER1 0xFFE1002C 357*819833afSPeter Tyser 358*819833afSPeter Tyser /* Serial I/O with FIFO */ 359*819833afSPeter Tyser #define SIMDR 0xFFE20000 360*819833afSPeter Tyser #define SISCR 0xFFE20002 361*819833afSPeter Tyser #define SITDAR 0xFFE20004 362*819833afSPeter Tyser #define SIRDAR 0xFFE20006 363*819833afSPeter Tyser #define SICDAR 0xFFE20008 364*819833afSPeter Tyser #define SICTR 0xFFE2000C 365*819833afSPeter Tyser #define SIFCTR 0xFFE20010 366*819833afSPeter Tyser #define SISTR 0xFFE20014 367*819833afSPeter Tyser #define SIIER 0xFFE20016 368*819833afSPeter Tyser #define SITCR 0xFFE20028 369*819833afSPeter Tyser #define SIRCR 0xFFE2002C 370*819833afSPeter Tyser #define SPICR 0xFFE20030 371*819833afSPeter Tyser 372*819833afSPeter Tyser /* Serial Protocol Interface */ 373*819833afSPeter Tyser #define SPCR 0xFFE50000 374*819833afSPeter Tyser #define SPSR 0xFFE50004 375*819833afSPeter Tyser #define SPSCR 0xFFE50008 376*819833afSPeter Tyser #define SPTBR 0xFFE5000C 377*819833afSPeter Tyser #define SPRBR 0xFFE50010 378*819833afSPeter Tyser 379*819833afSPeter Tyser /* Multimedia Card Interface */ 380*819833afSPeter Tyser #define CMDR0 0xFFE60000 381*819833afSPeter Tyser #define CMDR1 0xFFE60001 382*819833afSPeter Tyser #define CMDR2 0xFFE60002 383*819833afSPeter Tyser #define CMDR3 0xFFE60003 384*819833afSPeter Tyser #define CMDR4 0xFFE60004 385*819833afSPeter Tyser #define CMDR5 0xFFE60005 386*819833afSPeter Tyser #define CMDSTRT 0xFFE60006 387*819833afSPeter Tyser #define OPCR 0xFFE6000A 388*819833afSPeter Tyser #define CSTR 0xFFE6000B 389*819833afSPeter Tyser #define INTCR0 0xFFE6000C 390*819833afSPeter Tyser #define INTCR1 0xFFE6000D 391*819833afSPeter Tyser #define INTSTR0 0xFFE6000E 392*819833afSPeter Tyser #define INTSTR1 0xFFE6000F 393*819833afSPeter Tyser #define CLKON 0xFFE60010 394*819833afSPeter Tyser #define CTOCR 0xFFE60011 395*819833afSPeter Tyser #define TBCR 0xFFE60014 396*819833afSPeter Tyser #define MODER 0xFFE60016 397*819833afSPeter Tyser #define CMDTYR 0xFFE60018 398*819833afSPeter Tyser #define RSPTYR 0xFFE60019 399*819833afSPeter Tyser #define TBNCR 0xFFE6001A 400*819833afSPeter Tyser #define RSPR0 0xFFE60020 401*819833afSPeter Tyser #define RSPR1 0xFFE60021 402*819833afSPeter Tyser #define RSPR2 0xFFE60022 403*819833afSPeter Tyser #define RSPR3 0xFFE60023 404*819833afSPeter Tyser #define RSPR4 0xFFE60024 405*819833afSPeter Tyser #define RSPR5 0xFFE60025 406*819833afSPeter Tyser #define RSPR6 0xFFE60026 407*819833afSPeter Tyser #define RSPR7 0xFFE60027 408*819833afSPeter Tyser #define RSPR8 0xFFE60028 409*819833afSPeter Tyser #define RSPR9 0xFFE60029 410*819833afSPeter Tyser #define RSPR10 0xFFE6002A 411*819833afSPeter Tyser #define RSPR11 0xFFE6002B 412*819833afSPeter Tyser #define RSPR12 0xFFE6002C 413*819833afSPeter Tyser #define RSPR13 0xFFE6002D 414*819833afSPeter Tyser #define RSPR14 0xFFE6002E 415*819833afSPeter Tyser #define RSPR15 0xFFE6002F 416*819833afSPeter Tyser #define RSPR16 0xFFE60030 417*819833afSPeter Tyser #define RSPRD 0xFFE60031 418*819833afSPeter Tyser #define DTOUTR 0xFFE60032 419*819833afSPeter Tyser #define DR 0xFFE60040 420*819833afSPeter Tyser #define DMACR 0xFFE60044 421*819833afSPeter Tyser #define INTCR2 0xFFE60046 422*819833afSPeter Tyser #define INTSTR2 0xFFE60048 423*819833afSPeter Tyser 424*819833afSPeter Tyser /* Audio Codec Interface */ 425*819833afSPeter Tyser #define HACCR 0xFFE40008 426*819833afSPeter Tyser #define HACCSAR 0xFFE40020 427*819833afSPeter Tyser #define HACCSDR 0xFFE40024 428*819833afSPeter Tyser #define HACPCML 0xFFE40028 429*819833afSPeter Tyser #define HACPCMR 0xFFE4002C 430*819833afSPeter Tyser #define HACTIER 0xFFE40050 431*819833afSPeter Tyser #define HACTSR 0xFFE40054 432*819833afSPeter Tyser #define HACRIER 0xFFE40058 433*819833afSPeter Tyser #define HACRSR 0xFFE4005C 434*819833afSPeter Tyser #define HACACR 0xFFE40060 435*819833afSPeter Tyser 436*819833afSPeter Tyser /* Serial Sound Interface */ 437*819833afSPeter Tyser #define SSICR 0xFFE70000 438*819833afSPeter Tyser #define SSISR 0xFFE70004 439*819833afSPeter Tyser #define SSITDR 0xFFE70008 440*819833afSPeter Tyser #define SSIRDR 0xFFE7000C 441*819833afSPeter Tyser 442*819833afSPeter Tyser /* Flash memory Controller */ 443*819833afSPeter Tyser #define FLCMNCR 0xFFE90000 444*819833afSPeter Tyser #define FLCMDCR 0xFFE90004 445*819833afSPeter Tyser #define FLCMCDR 0xFFE90008 446*819833afSPeter Tyser #define FLADR 0xFFE9000C 447*819833afSPeter Tyser #define FLDATAR 0xFFE90010 448*819833afSPeter Tyser #define FLDTCNTR 0xFFE90014 449*819833afSPeter Tyser #define FLINTDMACR 0xFFE90018 450*819833afSPeter Tyser #define FLBSYTMR 0xFFE9001C 451*819833afSPeter Tyser #define FLBSYCNT 0xFFE90020 452*819833afSPeter Tyser #define FLTRCR 0xFFE9002C 453*819833afSPeter Tyser 454*819833afSPeter Tyser /* General Purpose I/O */ 455*819833afSPeter Tyser #define PACR 0xFFEA0000 456*819833afSPeter Tyser #define PBCR 0xFFEA0002 457*819833afSPeter Tyser #define PCCR 0xFFEA0004 458*819833afSPeter Tyser #define PDCR 0xFFEA0006 459*819833afSPeter Tyser #define PECR 0xFFEA0008 460*819833afSPeter Tyser #define PFCR 0xFFEA000A 461*819833afSPeter Tyser #define PGCR 0xFFEA000C 462*819833afSPeter Tyser #define PHCR 0xFFEA000E 463*819833afSPeter Tyser #define PJCR 0xFFEA0010 464*819833afSPeter Tyser #define PKCR 0xFFEA0012 465*819833afSPeter Tyser #define PLCR 0xFFEA0014 466*819833afSPeter Tyser #define PMCR 0xFFEA0016 467*819833afSPeter Tyser #define PADR 0xFFEA0020 468*819833afSPeter Tyser #define PBDR 0xFFEA0022 469*819833afSPeter Tyser #define PCDR 0xFFEA0024 470*819833afSPeter Tyser #define PDDR 0xFFEA0026 471*819833afSPeter Tyser #define PEDR 0xFFEA0028 472*819833afSPeter Tyser #define PFDR 0xFFEA002A 473*819833afSPeter Tyser #define PGDR 0xFFEA002C 474*819833afSPeter Tyser #define PHDR 0xFFEA002E 475*819833afSPeter Tyser #define PJDR 0xFFEA0030 476*819833afSPeter Tyser #define PKDR 0xFFEA0032 477*819833afSPeter Tyser #define PLDR 0xFFEA0034 478*819833afSPeter Tyser #define PMDR 0xFFEA0036 479*819833afSPeter Tyser #define PEPUPR 0xFFEA0048 480*819833afSPeter Tyser #define PHPUPR 0xFFEA004E 481*819833afSPeter Tyser #define PJPUPR 0xFFEA0050 482*819833afSPeter Tyser #define PKPUPR 0xFFEA0052 483*819833afSPeter Tyser #define PMPUPR 0xFFEA0056 484*819833afSPeter Tyser #define PPUPR1 0xFFEA0060 485*819833afSPeter Tyser #define PPUPR2 0xFFEA0062 486*819833afSPeter Tyser #define PMSELR 0xFFEA0080 487*819833afSPeter Tyser 488*819833afSPeter Tyser /* User Break Controller */ 489*819833afSPeter Tyser #define CBR0 0xFF200000 490*819833afSPeter Tyser #define CRR0 0xFF200004 491*819833afSPeter Tyser #define CAR0 0xFF200008 492*819833afSPeter Tyser #define CAMR0 0xFF20000C 493*819833afSPeter Tyser #define CBR1 0xFF200020 494*819833afSPeter Tyser #define CRR1 0xFF200024 495*819833afSPeter Tyser #define CAR1 0xFF200028 496*819833afSPeter Tyser #define CAMR1 0xFF20002C 497*819833afSPeter Tyser #define CDR1 0xFF200030 498*819833afSPeter Tyser #define CDMR1 0xFF200034 499*819833afSPeter Tyser #define CETR1 0xFF200038 500*819833afSPeter Tyser #define CCMFR 0xFF200600 501*819833afSPeter Tyser #define CBCR 0xFF200620 502*819833afSPeter Tyser 503*819833afSPeter Tyser #endif /* _ASM_CPU_SH7780_H_ */ 504