1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_CPU_SH7757_H_ 22 #define _ASM_CPU_SH7757_H_ 23 24 #define CCR 0xFF00001C 25 #define WTCNT 0xFFCC0000 26 #define CCR_CACHE_INIT 0x0000090b 27 #define CACHE_OC_NUM_WAYS 1 28 29 #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 30 /* MMU */ 31 struct mmu_regs { 32 unsigned int reserved[4]; 33 unsigned int mmucr; 34 }; 35 #define MMU_BASE ((struct mmu_regs *)0xff000000) 36 37 /* Watchdog */ 38 #define WTCSR0 0xffcc0002 39 #define WRSTCSR_R 0xffcc0003 40 #define WRSTCSR_W 0xffcc0002 41 #define WTCSR_PREFIX 0xa500 42 #define WRSTCSR_PREFIX 0x6900 43 #define WRSTCSR_WOVF_PREFIX 0x9600 44 45 /* SCIF */ 46 #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 47 #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 48 #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 49 50 /* SerMux */ 51 #define SMR0 0xfe470000 52 53 /* TMU0 */ 54 #define TSTR 0xFE430004 55 #define TOCR 0xFE430000 56 #define TSTR0 0xFE430004 57 #define TCOR0 0xFE430008 58 #define TCNT0 0xFE43000C 59 #define TCR0 0xFE430010 60 #define TCOR1 0xFE430014 61 #define TCNT1 0xFE430018 62 #define TCR1 0xFE43001C 63 #define TCOR2 0xFE430020 64 #define TCNT2 0xFE430024 65 #define TCR2 0xFE430028 66 #define TCPR2 0xFE43002C 67 68 /* ETHER, GETHER MAC address */ 69 struct ether_mac_regs { 70 unsigned int reserved[114]; 71 unsigned int mahr; 72 unsigned int reserved2; 73 unsigned int malr; 74 }; 75 #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 76 #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 77 #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 78 #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 79 80 /* GETHER */ 81 struct gether_control_regs { 82 unsigned int gbecont; 83 }; 84 #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 85 #define GBECONT_RMII1 0x00020000 86 #define GBECONT_RMII0 0x00010000 87 88 /* USB0/1 */ 89 struct usb_common_regs { 90 unsigned short reserved[129]; 91 unsigned short suspmode; 92 }; 93 #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 94 #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 95 96 struct usb0_phy_regs { 97 unsigned short reset; 98 unsigned short reserved[4]; 99 unsigned short portsel; 100 }; 101 #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 102 103 struct usb1_port_regs { 104 unsigned int port1sel; 105 unsigned int reserved; 106 unsigned int usb1intsts; 107 }; 108 #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 109 110 struct usb1_alignment_regs { 111 unsigned int ehcidatac; /* 0xfe4fe018 */ 112 unsigned int reserved[63]; 113 unsigned int ohcidatac; 114 }; 115 #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 116 117 /* GCTRL, GRA */ 118 struct gctrl_regs { 119 unsigned int wprotect; 120 unsigned int gplldiv; 121 unsigned int gracr2; /* GRA */ 122 unsigned int gracr3; /* GRA */ 123 unsigned int reserved[4]; 124 unsigned int fcntcr1; 125 unsigned int fcntcr2; 126 unsigned int reserved2[2]; 127 unsigned int gpll1div; 128 unsigned int vcompsel; 129 unsigned int reserved3[62]; 130 unsigned int fdlmon; 131 unsigned int reserved4[2]; 132 unsigned int flcrmon; 133 unsigned int reserved5[944]; 134 unsigned int spibootcan; 135 }; 136 #define GCTRL_BASE ((struct gctrl_regs *)0xffc10000) 137 138 /* PCIe setup */ 139 struct pcie_setup_regs { 140 unsigned int pbictl0; 141 unsigned int gradevctl; 142 unsigned int reserved[2]; 143 unsigned int bmcinf[6]; 144 unsigned int reserved2[118]; 145 unsigned int idset[2]; 146 unsigned int subidset; 147 unsigned int reserved3[2]; 148 unsigned int linkconfset[4]; 149 unsigned int trsid; 150 unsigned int reserved4[6]; 151 unsigned int toutset; 152 unsigned int reserved5[7]; 153 unsigned int lad0; 154 unsigned int ladmsk0; 155 unsigned int lad1; 156 unsigned int ladmsk1; 157 unsigned int lad2; 158 unsigned int ladmsk2; 159 unsigned int lad3; 160 unsigned int ladmsk3; 161 unsigned int lad4; 162 unsigned int ladmsk4; 163 unsigned int lad5; 164 unsigned int ladmsk5; 165 unsigned int reserved6[94]; 166 unsigned int vdmrxvid[2]; 167 unsigned int reserved7; 168 unsigned int pbiintfr; 169 unsigned int pbiinten; 170 unsigned int msimap; 171 unsigned int barmap; 172 unsigned int baracsize; 173 unsigned int advserest; 174 unsigned int pbictl3; 175 unsigned int reserved8[8]; 176 unsigned int pbictl1; 177 unsigned int scratch0; 178 unsigned int reserved9[6]; 179 unsigned int pbictl2; 180 unsigned int reserved10; 181 unsigned int pbirev; 182 }; 183 #define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000) 184 185 struct pcie_system_bus_regs { 186 unsigned int reserved[3]; 187 unsigned int endictl0; 188 unsigned int endictl1; 189 }; 190 #define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600) 191 192 193 /* PCIe-Bridge */ 194 struct pciebrg_regs { 195 unsigned short ctrl_h8s; 196 unsigned short reserved[7]; 197 unsigned short cp_addr; 198 unsigned short reserved2; 199 unsigned short cp_data; 200 unsigned short reserved3; 201 unsigned short cp_ctrl; 202 }; 203 #define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000) 204 205 /* CPU version */ 206 #define CCN_PRR 0xff000044 207 #define prr_mask(_val) ((_val >> 4) & 0xff) 208 #define PRR_SH7757_B0 0x10 209 #define PRR_SH7757_C0 0x11 210 211 #define is_sh7757_b0(_val) \ 212 ({ \ 213 int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \ 214 __ret; \ 215 }) 216 #endif /* ifndef __ASSEMBLY__ */ 217 218 #endif /* _ASM_CPU_SH7757_H_ */ 219