1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_CPU_SH7757_H_ 22 #define _ASM_CPU_SH7757_H_ 23 24 #define CCR 0xFF00001C 25 #define WTCNT 0xFFCC0000 26 #define CCR_CACHE_INIT 0x0000090b 27 #define CACHE_OC_NUM_WAYS 1 28 29 #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 30 /* MMU */ 31 struct mmu_regs { 32 unsigned int reserved[4]; 33 unsigned int mmucr; 34 }; 35 #define MMU_BASE ((struct mmu_regs *)0xff000000) 36 37 /* Watchdog */ 38 #define WTCSR0 0xffcc0002 39 #define WRSTCSR_R 0xffcc0003 40 #define WRSTCSR_W 0xffcc0002 41 #define WTCSR_PREFIX 0xa500 42 #define WRSTCSR_PREFIX 0x6900 43 #define WRSTCSR_WOVF_PREFIX 0x9600 44 45 /* SCIF */ 46 #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 47 #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 48 #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 49 50 /* SerMux */ 51 #define SMR0 0xfe470000 52 53 /* TMU0 */ 54 #define TMU_BASE 0xFE430000 55 56 /* ETHER, GETHER MAC address */ 57 struct ether_mac_regs { 58 unsigned int reserved[114]; 59 unsigned int mahr; 60 unsigned int reserved2; 61 unsigned int malr; 62 }; 63 #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 64 #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 65 #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 66 #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 67 68 /* GETHER */ 69 struct gether_control_regs { 70 unsigned int gbecont; 71 }; 72 #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 73 #define GBECONT_RMII1 0x00020000 74 #define GBECONT_RMII0 0x00010000 75 76 /* USB0/1 */ 77 struct usb_common_regs { 78 unsigned short reserved[129]; 79 unsigned short suspmode; 80 }; 81 #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 82 #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 83 84 struct usb0_phy_regs { 85 unsigned short reset; 86 unsigned short reserved[4]; 87 unsigned short portsel; 88 }; 89 #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 90 91 struct usb1_port_regs { 92 unsigned int port1sel; 93 unsigned int reserved; 94 unsigned int usb1intsts; 95 }; 96 #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 97 98 struct usb1_alignment_regs { 99 unsigned int ehcidatac; /* 0xfe4fe018 */ 100 unsigned int reserved[63]; 101 unsigned int ohcidatac; 102 }; 103 #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 104 105 /* GCTRL, GRA */ 106 struct gctrl_regs { 107 unsigned int wprotect; 108 unsigned int gplldiv; 109 unsigned int gracr2; /* GRA */ 110 unsigned int gracr3; /* GRA */ 111 unsigned int reserved[4]; 112 unsigned int fcntcr1; 113 unsigned int fcntcr2; 114 unsigned int reserved2[2]; 115 unsigned int gpll1div; 116 unsigned int vcompsel; 117 unsigned int reserved3[62]; 118 unsigned int fdlmon; 119 unsigned int reserved4[2]; 120 unsigned int flcrmon; 121 unsigned int reserved5[944]; 122 unsigned int spibootcan; 123 }; 124 #define GCTRL_BASE ((struct gctrl_regs *)0xffc10000) 125 126 /* PCIe setup */ 127 struct pcie_setup_regs { 128 unsigned int pbictl0; 129 unsigned int gradevctl; 130 unsigned int reserved[2]; 131 unsigned int bmcinf[6]; 132 unsigned int reserved2[118]; 133 unsigned int idset[2]; 134 unsigned int subidset; 135 unsigned int reserved3[2]; 136 unsigned int linkconfset[4]; 137 unsigned int trsid; 138 unsigned int reserved4[6]; 139 unsigned int toutset; 140 unsigned int reserved5[7]; 141 unsigned int lad0; 142 unsigned int ladmsk0; 143 unsigned int lad1; 144 unsigned int ladmsk1; 145 unsigned int lad2; 146 unsigned int ladmsk2; 147 unsigned int lad3; 148 unsigned int ladmsk3; 149 unsigned int lad4; 150 unsigned int ladmsk4; 151 unsigned int lad5; 152 unsigned int ladmsk5; 153 unsigned int reserved6[94]; 154 unsigned int vdmrxvid[2]; 155 unsigned int reserved7; 156 unsigned int pbiintfr; 157 unsigned int pbiinten; 158 unsigned int msimap; 159 unsigned int barmap; 160 unsigned int baracsize; 161 unsigned int advserest; 162 unsigned int pbictl3; 163 unsigned int reserved8[8]; 164 unsigned int pbictl1; 165 unsigned int scratch0; 166 unsigned int reserved9[6]; 167 unsigned int pbictl2; 168 unsigned int reserved10; 169 unsigned int pbirev; 170 }; 171 #define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000) 172 173 struct pcie_system_bus_regs { 174 unsigned int reserved[3]; 175 unsigned int endictl0; 176 unsigned int endictl1; 177 }; 178 #define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600) 179 180 181 /* PCIe-Bridge */ 182 struct pciebrg_regs { 183 unsigned short ctrl_h8s; 184 unsigned short reserved[7]; 185 unsigned short cp_addr; 186 unsigned short reserved2; 187 unsigned short cp_data; 188 unsigned short reserved3; 189 unsigned short cp_ctrl; 190 }; 191 #define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000) 192 193 /* CPU version */ 194 #define CCN_PRR 0xff000044 195 #define prr_mask(_val) ((_val >> 4) & 0xff) 196 #define PRR_SH7757_B0 0x10 197 #define PRR_SH7757_C0 0x11 198 199 #define is_sh7757_b0(_val) \ 200 ({ \ 201 int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \ 202 __ret; \ 203 }) 204 #endif /* ifndef __ASSEMBLY__ */ 205 206 #endif /* _ASM_CPU_SH7757_H_ */ 207