1*320cf350SYoshihiro Shimoda /* 2*320cf350SYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 3*320cf350SYoshihiro Shimoda * 4*320cf350SYoshihiro Shimoda * SPDX-License-Identifier: GPL-2.0+ 5*320cf350SYoshihiro Shimoda */ 6*320cf350SYoshihiro Shimoda 7*320cf350SYoshihiro Shimoda #ifndef _ASM_CPU_SH7753_H_ 8*320cf350SYoshihiro Shimoda #define _ASM_CPU_SH7753_H_ 9*320cf350SYoshihiro Shimoda 10*320cf350SYoshihiro Shimoda #define CCR 0xFF00001C 11*320cf350SYoshihiro Shimoda #define WTCNT 0xFFCC0000 12*320cf350SYoshihiro Shimoda #define CCR_CACHE_INIT 0x0000090b 13*320cf350SYoshihiro Shimoda #define CACHE_OC_NUM_WAYS 1 14*320cf350SYoshihiro Shimoda 15*320cf350SYoshihiro Shimoda #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 16*320cf350SYoshihiro Shimoda /* MMU */ 17*320cf350SYoshihiro Shimoda struct mmu_regs { 18*320cf350SYoshihiro Shimoda unsigned int reserved[4]; 19*320cf350SYoshihiro Shimoda unsigned int mmucr; 20*320cf350SYoshihiro Shimoda }; 21*320cf350SYoshihiro Shimoda #define MMU_BASE ((struct mmu_regs *)0xff000000) 22*320cf350SYoshihiro Shimoda 23*320cf350SYoshihiro Shimoda /* Watchdog */ 24*320cf350SYoshihiro Shimoda #define WTCSR0 0xffcc0002 25*320cf350SYoshihiro Shimoda #define WRSTCSR_R 0xffcc0003 26*320cf350SYoshihiro Shimoda #define WRSTCSR_W 0xffcc0002 27*320cf350SYoshihiro Shimoda #define WTCSR_PREFIX 0xa500 28*320cf350SYoshihiro Shimoda #define WRSTCSR_PREFIX 0x6900 29*320cf350SYoshihiro Shimoda #define WRSTCSR_WOVF_PREFIX 0x9600 30*320cf350SYoshihiro Shimoda 31*320cf350SYoshihiro Shimoda /* SCIF */ 32*320cf350SYoshihiro Shimoda #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 33*320cf350SYoshihiro Shimoda #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 34*320cf350SYoshihiro Shimoda #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 35*320cf350SYoshihiro Shimoda 36*320cf350SYoshihiro Shimoda /* TMU0 */ 37*320cf350SYoshihiro Shimoda #define TMU_BASE 0xFE430000 38*320cf350SYoshihiro Shimoda 39*320cf350SYoshihiro Shimoda /* ETHER, GETHER MAC address */ 40*320cf350SYoshihiro Shimoda struct ether_mac_regs { 41*320cf350SYoshihiro Shimoda unsigned int reserved[114]; 42*320cf350SYoshihiro Shimoda unsigned int mahr; 43*320cf350SYoshihiro Shimoda unsigned int reserved2; 44*320cf350SYoshihiro Shimoda unsigned int malr; 45*320cf350SYoshihiro Shimoda }; 46*320cf350SYoshihiro Shimoda #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 47*320cf350SYoshihiro Shimoda #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 48*320cf350SYoshihiro Shimoda #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 49*320cf350SYoshihiro Shimoda #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 50*320cf350SYoshihiro Shimoda 51*320cf350SYoshihiro Shimoda /* GETHER */ 52*320cf350SYoshihiro Shimoda struct gether_control_regs { 53*320cf350SYoshihiro Shimoda unsigned int gbecont; 54*320cf350SYoshihiro Shimoda }; 55*320cf350SYoshihiro Shimoda #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 56*320cf350SYoshihiro Shimoda #define GBECONT_RMII1 0x00020000 57*320cf350SYoshihiro Shimoda #define GBECONT_RMII0 0x00010000 58*320cf350SYoshihiro Shimoda 59*320cf350SYoshihiro Shimoda /* SerMux */ 60*320cf350SYoshihiro Shimoda struct sermux_regs { 61*320cf350SYoshihiro Shimoda unsigned char smr0; 62*320cf350SYoshihiro Shimoda unsigned char smr1; 63*320cf350SYoshihiro Shimoda unsigned char smr2; 64*320cf350SYoshihiro Shimoda unsigned char smr3; 65*320cf350SYoshihiro Shimoda unsigned char smr4; 66*320cf350SYoshihiro Shimoda unsigned char smr5; 67*320cf350SYoshihiro Shimoda }; 68*320cf350SYoshihiro Shimoda #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) 69*320cf350SYoshihiro Shimoda 70*320cf350SYoshihiro Shimoda 71*320cf350SYoshihiro Shimoda /* USB0/1 */ 72*320cf350SYoshihiro Shimoda struct usb_common_regs { 73*320cf350SYoshihiro Shimoda unsigned short reserved[129]; 74*320cf350SYoshihiro Shimoda unsigned short suspmode; 75*320cf350SYoshihiro Shimoda }; 76*320cf350SYoshihiro Shimoda #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 77*320cf350SYoshihiro Shimoda #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 78*320cf350SYoshihiro Shimoda 79*320cf350SYoshihiro Shimoda struct usb0_phy_regs { 80*320cf350SYoshihiro Shimoda unsigned short reset; 81*320cf350SYoshihiro Shimoda unsigned short reserved[4]; 82*320cf350SYoshihiro Shimoda unsigned short portsel; 83*320cf350SYoshihiro Shimoda }; 84*320cf350SYoshihiro Shimoda #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 85*320cf350SYoshihiro Shimoda 86*320cf350SYoshihiro Shimoda struct usb1_port_regs { 87*320cf350SYoshihiro Shimoda unsigned int port1sel; 88*320cf350SYoshihiro Shimoda unsigned int reserved; 89*320cf350SYoshihiro Shimoda unsigned int usb1intsts; 90*320cf350SYoshihiro Shimoda }; 91*320cf350SYoshihiro Shimoda #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 92*320cf350SYoshihiro Shimoda 93*320cf350SYoshihiro Shimoda struct usb1_alignment_regs { 94*320cf350SYoshihiro Shimoda unsigned int ehcidatac; /* 0xfe4fe018 */ 95*320cf350SYoshihiro Shimoda unsigned int reserved[63]; 96*320cf350SYoshihiro Shimoda unsigned int ohcidatac; 97*320cf350SYoshihiro Shimoda }; 98*320cf350SYoshihiro Shimoda #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 99*320cf350SYoshihiro Shimoda 100*320cf350SYoshihiro Shimoda /* GPIO */ 101*320cf350SYoshihiro Shimoda struct gpio_regs { 102*320cf350SYoshihiro Shimoda unsigned short pacr; 103*320cf350SYoshihiro Shimoda unsigned short pbcr; 104*320cf350SYoshihiro Shimoda unsigned short pccr; 105*320cf350SYoshihiro Shimoda unsigned short pdcr; 106*320cf350SYoshihiro Shimoda unsigned short pecr; 107*320cf350SYoshihiro Shimoda unsigned short pfcr; 108*320cf350SYoshihiro Shimoda unsigned short pgcr; 109*320cf350SYoshihiro Shimoda unsigned short phcr; 110*320cf350SYoshihiro Shimoda unsigned short picr; 111*320cf350SYoshihiro Shimoda unsigned short pjcr; 112*320cf350SYoshihiro Shimoda unsigned short pkcr; 113*320cf350SYoshihiro Shimoda unsigned short plcr; 114*320cf350SYoshihiro Shimoda unsigned short pmcr; 115*320cf350SYoshihiro Shimoda unsigned short pncr; 116*320cf350SYoshihiro Shimoda unsigned short pocr; 117*320cf350SYoshihiro Shimoda unsigned short reserved; 118*320cf350SYoshihiro Shimoda unsigned short pqcr; 119*320cf350SYoshihiro Shimoda unsigned short prcr; 120*320cf350SYoshihiro Shimoda unsigned short pscr; 121*320cf350SYoshihiro Shimoda unsigned short ptcr; 122*320cf350SYoshihiro Shimoda unsigned short pucr; 123*320cf350SYoshihiro Shimoda unsigned short pvcr; 124*320cf350SYoshihiro Shimoda unsigned short pwcr; 125*320cf350SYoshihiro Shimoda unsigned short pxcr; 126*320cf350SYoshihiro Shimoda unsigned short pycr; 127*320cf350SYoshihiro Shimoda unsigned short pzcr; 128*320cf350SYoshihiro Shimoda unsigned char padr; 129*320cf350SYoshihiro Shimoda unsigned char reserved_a; 130*320cf350SYoshihiro Shimoda unsigned char pbdr; 131*320cf350SYoshihiro Shimoda unsigned char reserved_b; 132*320cf350SYoshihiro Shimoda unsigned char pcdr; 133*320cf350SYoshihiro Shimoda unsigned char reserved_c; 134*320cf350SYoshihiro Shimoda unsigned char pddr; 135*320cf350SYoshihiro Shimoda unsigned char reserved_d; 136*320cf350SYoshihiro Shimoda unsigned char pedr; 137*320cf350SYoshihiro Shimoda unsigned char reserved_e; 138*320cf350SYoshihiro Shimoda unsigned char pfdr; 139*320cf350SYoshihiro Shimoda unsigned char reserved_f; 140*320cf350SYoshihiro Shimoda unsigned char pgdr; 141*320cf350SYoshihiro Shimoda unsigned char reserved_g; 142*320cf350SYoshihiro Shimoda unsigned char phdr; 143*320cf350SYoshihiro Shimoda unsigned char reserved_h; 144*320cf350SYoshihiro Shimoda unsigned char pidr; 145*320cf350SYoshihiro Shimoda unsigned char reserved_i; 146*320cf350SYoshihiro Shimoda unsigned char pjdr; 147*320cf350SYoshihiro Shimoda unsigned char reserved_j; 148*320cf350SYoshihiro Shimoda unsigned char pkdr; 149*320cf350SYoshihiro Shimoda unsigned char reserved_k; 150*320cf350SYoshihiro Shimoda unsigned char pldr; 151*320cf350SYoshihiro Shimoda unsigned char reserved_l; 152*320cf350SYoshihiro Shimoda unsigned char pmdr; 153*320cf350SYoshihiro Shimoda unsigned char reserved_m; 154*320cf350SYoshihiro Shimoda unsigned char pndr; 155*320cf350SYoshihiro Shimoda unsigned char reserved_n; 156*320cf350SYoshihiro Shimoda unsigned char podr; 157*320cf350SYoshihiro Shimoda unsigned char reserved_o; 158*320cf350SYoshihiro Shimoda unsigned char ppdr; 159*320cf350SYoshihiro Shimoda unsigned char reserved_p; 160*320cf350SYoshihiro Shimoda unsigned char pqdr; 161*320cf350SYoshihiro Shimoda unsigned char reserved_q; 162*320cf350SYoshihiro Shimoda unsigned char prdr; 163*320cf350SYoshihiro Shimoda unsigned char reserved_r; 164*320cf350SYoshihiro Shimoda unsigned char psdr; 165*320cf350SYoshihiro Shimoda unsigned char reserved_s; 166*320cf350SYoshihiro Shimoda unsigned char ptdr; 167*320cf350SYoshihiro Shimoda unsigned char reserved_t; 168*320cf350SYoshihiro Shimoda unsigned char pudr; 169*320cf350SYoshihiro Shimoda unsigned char reserved_u; 170*320cf350SYoshihiro Shimoda unsigned char pvdr; 171*320cf350SYoshihiro Shimoda unsigned char reserved_v; 172*320cf350SYoshihiro Shimoda unsigned char pwdr; 173*320cf350SYoshihiro Shimoda unsigned char reserved_w; 174*320cf350SYoshihiro Shimoda unsigned char pxdr; 175*320cf350SYoshihiro Shimoda unsigned char reserved_x; 176*320cf350SYoshihiro Shimoda unsigned char pydr; 177*320cf350SYoshihiro Shimoda unsigned char reserved_y; 178*320cf350SYoshihiro Shimoda unsigned char pzdr; 179*320cf350SYoshihiro Shimoda unsigned char reserved_z; 180*320cf350SYoshihiro Shimoda unsigned short ncer; 181*320cf350SYoshihiro Shimoda unsigned short ncmcr; 182*320cf350SYoshihiro Shimoda unsigned short nccsr; 183*320cf350SYoshihiro Shimoda unsigned char reserved2[2]; 184*320cf350SYoshihiro Shimoda unsigned short psel0; /* +0x70 */ 185*320cf350SYoshihiro Shimoda unsigned short psel1; 186*320cf350SYoshihiro Shimoda unsigned short psel2; 187*320cf350SYoshihiro Shimoda unsigned short psel3; 188*320cf350SYoshihiro Shimoda unsigned short psel4; 189*320cf350SYoshihiro Shimoda unsigned short psel5; 190*320cf350SYoshihiro Shimoda unsigned short psel6; 191*320cf350SYoshihiro Shimoda unsigned short reserved3[2]; 192*320cf350SYoshihiro Shimoda unsigned short psel7; 193*320cf350SYoshihiro Shimoda }; 194*320cf350SYoshihiro Shimoda #define GPIO_BASE ((struct gpio_regs *)0xffec0000) 195*320cf350SYoshihiro Shimoda 196*320cf350SYoshihiro Shimoda #endif /* ifndef __ASSEMBLY__ */ 197*320cf350SYoshihiro Shimoda #endif /* _ASM_CPU_SH7753_H_ */ 198