1*1a2621baSYoshihiro Shimoda /* 2*1a2621baSYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 3*1a2621baSYoshihiro Shimoda * 4*1a2621baSYoshihiro Shimoda * This program is free software; you can redistribute it and/or 5*1a2621baSYoshihiro Shimoda * modify it under the terms of the GNU General Public License as 6*1a2621baSYoshihiro Shimoda * published by the Free Software Foundation; either version 2 of 7*1a2621baSYoshihiro Shimoda * the License, or (at your option) any later version. 8*1a2621baSYoshihiro Shimoda * 9*1a2621baSYoshihiro Shimoda * This program is distributed in the hope that it will be useful, 10*1a2621baSYoshihiro Shimoda * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*1a2621baSYoshihiro Shimoda * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*1a2621baSYoshihiro Shimoda * GNU General Public License for more details. 13*1a2621baSYoshihiro Shimoda * 14*1a2621baSYoshihiro Shimoda * You should have received a copy of the GNU General Public License 15*1a2621baSYoshihiro Shimoda * along with this program; if not, write to the Free Software 16*1a2621baSYoshihiro Shimoda * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17*1a2621baSYoshihiro Shimoda * MA 02111-1307 USA 18*1a2621baSYoshihiro Shimoda * 19*1a2621baSYoshihiro Shimoda */ 20*1a2621baSYoshihiro Shimoda 21*1a2621baSYoshihiro Shimoda #ifndef _ASM_CPU_SH7752_H_ 22*1a2621baSYoshihiro Shimoda #define _ASM_CPU_SH7752_H_ 23*1a2621baSYoshihiro Shimoda 24*1a2621baSYoshihiro Shimoda #define CCR 0xFF00001C 25*1a2621baSYoshihiro Shimoda #define WTCNT 0xFFCC0000 26*1a2621baSYoshihiro Shimoda #define CCR_CACHE_INIT 0x0000090b 27*1a2621baSYoshihiro Shimoda #define CACHE_OC_NUM_WAYS 1 28*1a2621baSYoshihiro Shimoda 29*1a2621baSYoshihiro Shimoda #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 30*1a2621baSYoshihiro Shimoda /* MMU */ 31*1a2621baSYoshihiro Shimoda struct mmu_regs { 32*1a2621baSYoshihiro Shimoda unsigned int reserved[4]; 33*1a2621baSYoshihiro Shimoda unsigned int mmucr; 34*1a2621baSYoshihiro Shimoda }; 35*1a2621baSYoshihiro Shimoda #define MMU_BASE ((struct mmu_regs *)0xff000000) 36*1a2621baSYoshihiro Shimoda 37*1a2621baSYoshihiro Shimoda /* Watchdog */ 38*1a2621baSYoshihiro Shimoda #define WTCSR0 0xffcc0002 39*1a2621baSYoshihiro Shimoda #define WRSTCSR_R 0xffcc0003 40*1a2621baSYoshihiro Shimoda #define WRSTCSR_W 0xffcc0002 41*1a2621baSYoshihiro Shimoda #define WTCSR_PREFIX 0xa500 42*1a2621baSYoshihiro Shimoda #define WRSTCSR_PREFIX 0x6900 43*1a2621baSYoshihiro Shimoda #define WRSTCSR_WOVF_PREFIX 0x9600 44*1a2621baSYoshihiro Shimoda 45*1a2621baSYoshihiro Shimoda /* SCIF */ 46*1a2621baSYoshihiro Shimoda #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 47*1a2621baSYoshihiro Shimoda #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 48*1a2621baSYoshihiro Shimoda #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 49*1a2621baSYoshihiro Shimoda 50*1a2621baSYoshihiro Shimoda /* TMU0 */ 51*1a2621baSYoshihiro Shimoda #define TMU_BASE 0xFE430000 52*1a2621baSYoshihiro Shimoda 53*1a2621baSYoshihiro Shimoda /* ETHER, GETHER MAC address */ 54*1a2621baSYoshihiro Shimoda struct ether_mac_regs { 55*1a2621baSYoshihiro Shimoda unsigned int reserved[114]; 56*1a2621baSYoshihiro Shimoda unsigned int mahr; 57*1a2621baSYoshihiro Shimoda unsigned int reserved2; 58*1a2621baSYoshihiro Shimoda unsigned int malr; 59*1a2621baSYoshihiro Shimoda }; 60*1a2621baSYoshihiro Shimoda #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 61*1a2621baSYoshihiro Shimoda #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 62*1a2621baSYoshihiro Shimoda #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 63*1a2621baSYoshihiro Shimoda #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 64*1a2621baSYoshihiro Shimoda 65*1a2621baSYoshihiro Shimoda /* GETHER */ 66*1a2621baSYoshihiro Shimoda struct gether_control_regs { 67*1a2621baSYoshihiro Shimoda unsigned int gbecont; 68*1a2621baSYoshihiro Shimoda }; 69*1a2621baSYoshihiro Shimoda #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 70*1a2621baSYoshihiro Shimoda #define GBECONT_RMII1 0x00020000 71*1a2621baSYoshihiro Shimoda #define GBECONT_RMII0 0x00010000 72*1a2621baSYoshihiro Shimoda 73*1a2621baSYoshihiro Shimoda /* SerMux */ 74*1a2621baSYoshihiro Shimoda struct sermux_regs { 75*1a2621baSYoshihiro Shimoda unsigned char smr0; 76*1a2621baSYoshihiro Shimoda unsigned char smr1; 77*1a2621baSYoshihiro Shimoda unsigned char smr2; 78*1a2621baSYoshihiro Shimoda unsigned char smr3; 79*1a2621baSYoshihiro Shimoda unsigned char smr4; 80*1a2621baSYoshihiro Shimoda unsigned char smr5; 81*1a2621baSYoshihiro Shimoda }; 82*1a2621baSYoshihiro Shimoda #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) 83*1a2621baSYoshihiro Shimoda 84*1a2621baSYoshihiro Shimoda 85*1a2621baSYoshihiro Shimoda /* USB0/1 */ 86*1a2621baSYoshihiro Shimoda struct usb_common_regs { 87*1a2621baSYoshihiro Shimoda unsigned short reserved[129]; 88*1a2621baSYoshihiro Shimoda unsigned short suspmode; 89*1a2621baSYoshihiro Shimoda }; 90*1a2621baSYoshihiro Shimoda #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 91*1a2621baSYoshihiro Shimoda #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 92*1a2621baSYoshihiro Shimoda 93*1a2621baSYoshihiro Shimoda struct usb0_phy_regs { 94*1a2621baSYoshihiro Shimoda unsigned short reset; 95*1a2621baSYoshihiro Shimoda unsigned short reserved[4]; 96*1a2621baSYoshihiro Shimoda unsigned short portsel; 97*1a2621baSYoshihiro Shimoda }; 98*1a2621baSYoshihiro Shimoda #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 99*1a2621baSYoshihiro Shimoda 100*1a2621baSYoshihiro Shimoda struct usb1_port_regs { 101*1a2621baSYoshihiro Shimoda unsigned int port1sel; 102*1a2621baSYoshihiro Shimoda unsigned int reserved; 103*1a2621baSYoshihiro Shimoda unsigned int usb1intsts; 104*1a2621baSYoshihiro Shimoda }; 105*1a2621baSYoshihiro Shimoda #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 106*1a2621baSYoshihiro Shimoda 107*1a2621baSYoshihiro Shimoda struct usb1_alignment_regs { 108*1a2621baSYoshihiro Shimoda unsigned int ehcidatac; /* 0xfe4fe018 */ 109*1a2621baSYoshihiro Shimoda unsigned int reserved[63]; 110*1a2621baSYoshihiro Shimoda unsigned int ohcidatac; 111*1a2621baSYoshihiro Shimoda }; 112*1a2621baSYoshihiro Shimoda #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 113*1a2621baSYoshihiro Shimoda 114*1a2621baSYoshihiro Shimoda /* GPIO */ 115*1a2621baSYoshihiro Shimoda struct gpio_regs { 116*1a2621baSYoshihiro Shimoda unsigned short pacr; 117*1a2621baSYoshihiro Shimoda unsigned short pbcr; 118*1a2621baSYoshihiro Shimoda unsigned short pccr; 119*1a2621baSYoshihiro Shimoda unsigned short pdcr; 120*1a2621baSYoshihiro Shimoda unsigned short pecr; 121*1a2621baSYoshihiro Shimoda unsigned short pfcr; 122*1a2621baSYoshihiro Shimoda unsigned short pgcr; 123*1a2621baSYoshihiro Shimoda unsigned short phcr; 124*1a2621baSYoshihiro Shimoda unsigned short picr; 125*1a2621baSYoshihiro Shimoda unsigned short pjcr; 126*1a2621baSYoshihiro Shimoda unsigned short pkcr; 127*1a2621baSYoshihiro Shimoda unsigned short plcr; 128*1a2621baSYoshihiro Shimoda unsigned short pmcr; 129*1a2621baSYoshihiro Shimoda unsigned short pncr; 130*1a2621baSYoshihiro Shimoda unsigned short pocr; 131*1a2621baSYoshihiro Shimoda unsigned short reserved; 132*1a2621baSYoshihiro Shimoda unsigned short pqcr; 133*1a2621baSYoshihiro Shimoda unsigned short prcr; 134*1a2621baSYoshihiro Shimoda unsigned short pscr; 135*1a2621baSYoshihiro Shimoda unsigned short ptcr; 136*1a2621baSYoshihiro Shimoda unsigned short pucr; 137*1a2621baSYoshihiro Shimoda unsigned short pvcr; 138*1a2621baSYoshihiro Shimoda unsigned short pwcr; 139*1a2621baSYoshihiro Shimoda unsigned short pxcr; 140*1a2621baSYoshihiro Shimoda unsigned short pycr; 141*1a2621baSYoshihiro Shimoda unsigned short pzcr; 142*1a2621baSYoshihiro Shimoda unsigned char padr; 143*1a2621baSYoshihiro Shimoda unsigned char reserved_a; 144*1a2621baSYoshihiro Shimoda unsigned char pbdr; 145*1a2621baSYoshihiro Shimoda unsigned char reserved_b; 146*1a2621baSYoshihiro Shimoda unsigned char pcdr; 147*1a2621baSYoshihiro Shimoda unsigned char reserved_c; 148*1a2621baSYoshihiro Shimoda unsigned char pddr; 149*1a2621baSYoshihiro Shimoda unsigned char reserved_d; 150*1a2621baSYoshihiro Shimoda unsigned char pedr; 151*1a2621baSYoshihiro Shimoda unsigned char reserved_e; 152*1a2621baSYoshihiro Shimoda unsigned char pfdr; 153*1a2621baSYoshihiro Shimoda unsigned char reserved_f; 154*1a2621baSYoshihiro Shimoda unsigned char pgdr; 155*1a2621baSYoshihiro Shimoda unsigned char reserved_g; 156*1a2621baSYoshihiro Shimoda unsigned char phdr; 157*1a2621baSYoshihiro Shimoda unsigned char reserved_h; 158*1a2621baSYoshihiro Shimoda unsigned char pidr; 159*1a2621baSYoshihiro Shimoda unsigned char reserved_i; 160*1a2621baSYoshihiro Shimoda unsigned char pjdr; 161*1a2621baSYoshihiro Shimoda unsigned char reserved_j; 162*1a2621baSYoshihiro Shimoda unsigned char pkdr; 163*1a2621baSYoshihiro Shimoda unsigned char reserved_k; 164*1a2621baSYoshihiro Shimoda unsigned char pldr; 165*1a2621baSYoshihiro Shimoda unsigned char reserved_l; 166*1a2621baSYoshihiro Shimoda unsigned char pmdr; 167*1a2621baSYoshihiro Shimoda unsigned char reserved_m; 168*1a2621baSYoshihiro Shimoda unsigned char pndr; 169*1a2621baSYoshihiro Shimoda unsigned char reserved_n; 170*1a2621baSYoshihiro Shimoda unsigned char podr; 171*1a2621baSYoshihiro Shimoda unsigned char reserved_o; 172*1a2621baSYoshihiro Shimoda unsigned char ppdr; 173*1a2621baSYoshihiro Shimoda unsigned char reserved_p; 174*1a2621baSYoshihiro Shimoda unsigned char pqdr; 175*1a2621baSYoshihiro Shimoda unsigned char reserved_q; 176*1a2621baSYoshihiro Shimoda unsigned char prdr; 177*1a2621baSYoshihiro Shimoda unsigned char reserved_r; 178*1a2621baSYoshihiro Shimoda unsigned char psdr; 179*1a2621baSYoshihiro Shimoda unsigned char reserved_s; 180*1a2621baSYoshihiro Shimoda unsigned char ptdr; 181*1a2621baSYoshihiro Shimoda unsigned char reserved_t; 182*1a2621baSYoshihiro Shimoda unsigned char pudr; 183*1a2621baSYoshihiro Shimoda unsigned char reserved_u; 184*1a2621baSYoshihiro Shimoda unsigned char pvdr; 185*1a2621baSYoshihiro Shimoda unsigned char reserved_v; 186*1a2621baSYoshihiro Shimoda unsigned char pwdr; 187*1a2621baSYoshihiro Shimoda unsigned char reserved_w; 188*1a2621baSYoshihiro Shimoda unsigned char pxdr; 189*1a2621baSYoshihiro Shimoda unsigned char reserved_x; 190*1a2621baSYoshihiro Shimoda unsigned char pydr; 191*1a2621baSYoshihiro Shimoda unsigned char reserved_y; 192*1a2621baSYoshihiro Shimoda unsigned char pzdr; 193*1a2621baSYoshihiro Shimoda unsigned char reserved_z; 194*1a2621baSYoshihiro Shimoda unsigned short ncer; 195*1a2621baSYoshihiro Shimoda unsigned short ncmcr; 196*1a2621baSYoshihiro Shimoda unsigned short nccsr; 197*1a2621baSYoshihiro Shimoda unsigned char reserved2[2]; 198*1a2621baSYoshihiro Shimoda unsigned short psel0; /* +0x70 */ 199*1a2621baSYoshihiro Shimoda unsigned short psel1; 200*1a2621baSYoshihiro Shimoda unsigned short psel2; 201*1a2621baSYoshihiro Shimoda unsigned short psel3; 202*1a2621baSYoshihiro Shimoda unsigned short psel4; 203*1a2621baSYoshihiro Shimoda unsigned short psel5; 204*1a2621baSYoshihiro Shimoda unsigned short psel6; 205*1a2621baSYoshihiro Shimoda unsigned short reserved3[2]; 206*1a2621baSYoshihiro Shimoda unsigned short psel7; 207*1a2621baSYoshihiro Shimoda }; 208*1a2621baSYoshihiro Shimoda #define GPIO_BASE ((struct gpio_regs *)0xffec0000) 209*1a2621baSYoshihiro Shimoda 210*1a2621baSYoshihiro Shimoda #endif /* ifndef __ASSEMBLY__ */ 211*1a2621baSYoshihiro Shimoda #endif /* _ASM_CPU_SH7752_H_ */ 212