1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 4 * 5 * SH7750/SH7750S/SH7750R/SH7751/SH7751R 6 * Internal I/O register 7 */ 8 9 #ifndef _ASM_CPU_SH7750_H_ 10 #define _ASM_CPU_SH7750_H_ 11 12 #ifdef CONFIG_CPU_TYPE_R 13 #define CACHE_OC_NUM_WAYS 2 14 #define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ 15 #else 16 #define CACHE_OC_NUM_WAYS 1 17 #define CCR_CACHE_INIT 0x0000090B 18 #endif 19 20 /* OCN */ 21 #define PTEH 0xFF000000 22 #define PTEL 0xFF000004 23 #define TTB 0xFF000008 24 #define TEA 0xFF00000C 25 #define MMUCR 0xFF000010 26 #define BASRA 0xFF000014 27 #define BASRB 0xFF000018 28 #define CCR 0xFF00001C 29 #define TRA 0xFF000020 30 #define EXPEVT 0xFF000024 31 #define INTEVT 0xFF000028 32 #define PTEA 0xFF000034 33 #define QACR0 0xFF000038 34 #define QACR1 0xFF00003C 35 36 /* UBC */ 37 #define BARA 0xFF200000 38 #define BAMRA 0xFF200004 39 #define BBRA 0xFF200008 40 #define BARB 0xFF20000C 41 #define BAMRB 0xFF200010 42 #define BBRB 0xFF200014 43 #define BDRB 0xFF200018 44 #define BDMRB 0xFF20001C 45 #define BRCR 0xFF200020 46 47 /* BSC */ 48 #define BCR1 0xFF800000 49 #define BCR2 0xFF800004 50 #define BCR3 0xFF800050 51 #define BCR4 0xFE0A00F0 52 #define WCR1 0xFF800008 53 #define WCR2 0xFF80000C 54 #define WCR3 0xFF800010 55 #define MCR 0xFF800014 56 #define PCR 0xFF800018 57 #define RTCSR 0xFF80001C 58 #define RTCNT 0xFF800020 59 #define RTCOR 0xFF800024 60 #define RFCR 0xFF800028 61 #define PCTRA 0xFF80002C 62 #define PDTRA 0xFF800030 63 #define PCTRB 0xFF800040 64 #define PDTRB 0xFF800044 65 #define GPIOIC 0xFF800048 66 67 /* DMAC */ 68 #define SAR0 0xFFA00000 69 #define DAR0 0xFFA00004 70 #define DMATCR0 0xFFA00008 71 #define CHCR0 0xFFA0000C 72 #define SAR1 0xFFA00010 73 #define DAR1 0xFFA00014 74 #define DMATCR1 0xFFA00018 75 #define CHCR1 0xFFA0001C 76 #define SAR2 0xFFA00020 77 #define DAR2 0xFFA00024 78 #define DMATCR2 0xFFA00028 79 #define CHCR2 0xFFA0002C 80 #define SAR3 0xFFA00030 81 #define DAR3 0xFFA00034 82 #define DMATCR3 0xFFA00038 83 #define CHCR3 0xFFA0003C 84 #define DMAOR 0xFFA00040 85 #define SAR4 0xFFA00050 86 #define DAR4 0xFFA00054 87 #define DMATCR4 0xFFA00058 88 89 /* CPG */ 90 #define FRQCR 0xFFC00000 91 #define STBCR 0xFFC00004 92 #define WTCNT 0xFFC00008 93 #define WTCSR 0xFFC0000C 94 #define STBCR2 0xFFC00010 95 96 /* RTC */ 97 #define R64CNT 0xFFC80000 98 #define RSECCNT 0xFFC80004 99 #define RMINCNT 0xFFC80008 100 #define RHRCNT 0xFFC8000C 101 #define RWKCNT 0xFFC80010 102 #define RDAYCNT 0xFFC80014 103 #define RMONCNT 0xFFC80018 104 #define RYRCNT 0xFFC8001C 105 #define RSECAR 0xFFC80020 106 #define RMINAR 0xFFC80024 107 #define RHRAR 0xFFC80028 108 #define RWKAR 0xFFC8002C 109 #define RDAYAR 0xFFC80030 110 #define RMONAR 0xFFC80034 111 #define RCR1 0xFFC80038 112 #define RCR2 0xFFC8003C 113 #define RCR3 0xFFC80050 114 #define RYRAR 0xFFC80054 115 116 /* ICR */ 117 #define ICR 0xFFD00000 118 #define IPRA 0xFFD00004 119 #define IPRB 0xFFD00008 120 #define IPRC 0xFFD0000C 121 #define IPRD 0xFFD00010 122 #define INTPRI 0xFE080000 123 #define INTREQ 0xFE080020 124 #define INTMSK 0xFE080040 125 #define INTMSKCL 0xFE080060 126 127 /* CPG */ 128 #define CLKSTP 0xFE0A0000 129 #define CLKSTPCLR 0xFE0A0008 130 131 /* TMU */ 132 #define TMU_BASE 0xFFD80000 133 134 /* SCI */ 135 #define SCSMR1 0xFFE00000 136 #define SCF0_BASE SCSMR1 137 138 /* SCIF */ 139 #define SCSMR2 0xFFE80000 140 #define SCIF1_BASE SCSMR2 141 142 /* H-UDI */ 143 #define SDIR 0xFFF00000 144 #define SDDR 0xFFF00008 145 #define SDINT 0xFFF00014 146 147 #endif /* _ASM_CPU_SH7750_H_ */ 148