1 /* 2 * (C) Copyright 2008 Renesas Solutions Corp. 3 * 4 * SH7723 Internal I/O register 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef _ASM_CPU_SH7723_H_ 23 #define _ASM_CPU_SH7723_H_ 24 25 #define CACHE_OC_NUM_WAYS 4 26 #define CCR_CACHE_INIT 0x0000090d 27 28 /* EXP */ 29 #define TRA 0xFF000020 30 #define EXPEVT 0xFF000024 31 #define INTEVT 0xFF000028 32 33 /* MMU */ 34 #define PTEH 0xFF000000 35 #define PTEL 0xFF000004 36 #define TTB 0xFF000008 37 #define TEA 0xFF00000C 38 #define MMUCR 0xFF000010 39 #define PASCR 0xFF000070 40 #define IRMCR 0xFF000078 41 42 /* CACHE */ 43 #define CCR 0xFF00001C 44 #define RAMCR 0xFF000074 45 46 /* INTC */ 47 48 /* BSC */ 49 #define CMNCR 0xFEC10000 50 #define CS0BCR 0xFEC10004 51 #define CS2BCR 0xFEC10008 52 #define CS4BCR 0xFEC10010 53 #define CS5ABCR 0xFEC10014 54 #define CS5BBCR 0xFEC10018 55 #define CS6ABCR 0xFEC1001C 56 #define CS6BBCR 0xFEC10020 57 #define CS0WCR 0xFEC10024 58 #define CS2WCR 0xFEC10028 59 #define CS4WCR 0xFEC10030 60 #define CS5AWCR 0xFEC10034 61 #define CS5BWCR 0xFEC10038 62 #define CS6AWCR 0xFEC1003C 63 #define CS6BWCR 0xFEC10040 64 #define RBWTCNT 0xFEC10054 65 66 /* SBSC */ 67 #define SBSC_SDCR 0xFE400008 68 #define SBSC_SDWCR 0xFE40000C 69 #define SBSC_SDPCR 0xFE400010 70 #define SBSC_RTCSR 0xFE400014 71 #define SBSC_RTCNT 0xFE400018 72 #define SBSC_RTCOR 0xFE40001C 73 #define SBSC_RFCR 0xFE400020 74 75 /* DMAC */ 76 77 /* CPG */ 78 #define FRQCR 0xA4150000 79 #define VCLKCR 0xA4150004 80 #define SCLKACR 0xA4150008 81 #define SCLKBCR 0xA415000C 82 #define IRDACLKCR 0xA4150018 83 #define PLLCR 0xA4150024 84 #define DLLFRQ 0xA4150050 85 86 /* LOW POWER MODE */ 87 #define STBCR 0xA4150020 88 #define MSTPCR0 0xA4150030 89 #define MSTPCR1 0xA4150034 90 #define MSTPCR2 0xA4150038 91 92 /* RWDT */ 93 #define RWTCNT 0xA4520000 94 #define RWTCSR 0xA4520004 95 #define WTCNT RWTCNT 96 97 /* TMU */ 98 #define TSTR 0xFFD80004 99 #define TCOR0 0xFFD80008 100 #define TCNT0 0xFFD8000C 101 #define TCR0 0xFFD80010 102 #define TCOR1 0xFFD80014 103 #define TCNT1 0xFFD80018 104 #define TCR1 0xFFD8001C 105 #define TCOR2 0xFFD80020 106 #define TCNT2 0xFFD80024 107 #define TCR2 0xFFD80028 108 109 /* TPU */ 110 111 /* CMT */ 112 #define CMSTR 0xA44A0000 113 #define CMCSR 0xA44A0060 114 #define CMCNT 0xA44A0064 115 #define CMCOR 0xA44A0068 116 117 /* MSIOF */ 118 119 /* SCIF */ 120 #define SCIF0_BASE 0xFFE00000 121 #define SCIF1_BASE 0xFFE10000 122 #define SCIF2_BASE 0xFFE20000 123 #define SCIF3_BASE 0xa4e30000 124 #define SCIF4_BASE 0xa4e40000 125 #define SCIF5_BASE 0xa4e50000 126 127 /* RTC */ 128 /* IrDA */ 129 /* KEYSC */ 130 /* USB */ 131 /* IIC */ 132 /* FLCTL */ 133 /* VPU */ 134 /* VIO(CEU) */ 135 /* VIO(VEU) */ 136 /* VIO(BEU) */ 137 /* 2DG */ 138 /* LCDC */ 139 /* VOU */ 140 /* TSIF */ 141 /* SIU */ 142 /* ATAPI */ 143 144 /* PFC */ 145 #define PACR 0xA4050100 146 #define PBCR 0xA4050102 147 #define PCCR 0xA4050104 148 #define PDCR 0xA4050106 149 #define PECR 0xA4050108 150 #define PFCR 0xA405010A 151 #define PGCR 0xA405010C 152 #define PHCR 0xA405010E 153 #define PJCR 0xA4050110 154 #define PKCR 0xA4050112 155 #define PLCR 0xA4050114 156 #define PMCR 0xA4050116 157 #define PNCR 0xA4050118 158 #define PQCR 0xA405011A 159 #define PRCR 0xA405011C 160 #define PSCR 0xA405011E 161 #define PTCR 0xA4050140 162 #define PUCR 0xA4050142 163 #define PVCR 0xA4050144 164 #define PWCR 0xA4050146 165 #define PXCR 0xA4050148 166 #define PYCR 0xA405014A 167 #define PZCR 0xA405014C 168 #define PSELA 0xA405014E 169 #define PSELB 0xA4050150 170 #define PSELC 0xA4050152 171 #define PSELD 0xA4050154 172 #define HIZCRA 0xA4050158 173 #define HIZCRB 0xA405015A 174 #define HIZCRC 0xA405015C 175 #define HIZCRD 0xA405015E 176 #define MSELCRA 0xA4050180 177 #define MSELCRB 0xA4050182 178 #define PULCR 0xA4050184 179 #define DRVCRA 0xA405018A 180 #define DRVCRB 0xA405018C 181 182 /* I/O Port */ 183 #define PADR 0xA4050120 184 #define PBDR 0xA4050122 185 #define PCDR 0xA4050124 186 #define PDDR 0xA4050126 187 #define PEDR 0xA4050128 188 #define PFDR 0xA405012A 189 #define PGDR 0xA405012C 190 #define PHDR 0xA405012E 191 #define PJDR 0xA4050130 192 #define PKDR 0xA4050132 193 #define PLDR 0xA4050134 194 #define PMDR 0xA4050136 195 #define PNDR 0xA4050138 196 #define PQDR 0xA405013A 197 #define PRDR 0xA405013C 198 #define PSDR 0xA405013E 199 #define PTDR 0xA4050160 200 #define PUDR 0xA4050162 201 #define PVDR 0xA4050164 202 #define PWDR 0xA4050166 203 #define PYDR 0xA4050168 204 #define PZDR 0xA405016A 205 206 /* UBC */ 207 /* H-UDI */ 208 209 #endif /* _ASM_CPU_SH7723_H_ */ 210