1*819833afSPeter Tyser /* 2*819833afSPeter Tyser * (C) Copyright 2008 Renesas Solutions Corp. 3*819833afSPeter Tyser * 4*819833afSPeter Tyser * SH7723 Internal I/O register 5*819833afSPeter Tyser * 6*819833afSPeter Tyser * This program is free software; you can redistribute it and/or 7*819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 8*819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 9*819833afSPeter Tyser * the License, or (at your option) any later version. 10*819833afSPeter Tyser * 11*819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 12*819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*819833afSPeter Tyser * GNU General Public License for more details. 15*819833afSPeter Tyser * 16*819833afSPeter Tyser * You should have received a copy of the GNU General Public License 17*819833afSPeter Tyser * along with this program; if not, write to the Free Software 18*819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19*819833afSPeter Tyser * MA 02111-1307 USA 20*819833afSPeter Tyser */ 21*819833afSPeter Tyser 22*819833afSPeter Tyser #ifndef _ASM_CPU_SH7723_H_ 23*819833afSPeter Tyser #define _ASM_CPU_SH7723_H_ 24*819833afSPeter Tyser 25*819833afSPeter Tyser #define CACHE_OC_NUM_WAYS 4 26*819833afSPeter Tyser #define CCR_CACHE_INIT 0x0000090d 27*819833afSPeter Tyser 28*819833afSPeter Tyser /* EXP */ 29*819833afSPeter Tyser #define TRA 0xFF000020 30*819833afSPeter Tyser #define EXPEVT 0xFF000024 31*819833afSPeter Tyser #define INTEVT 0xFF000028 32*819833afSPeter Tyser 33*819833afSPeter Tyser /* MMU */ 34*819833afSPeter Tyser #define PTEH 0xFF000000 35*819833afSPeter Tyser #define PTEL 0xFF000004 36*819833afSPeter Tyser #define TTB 0xFF000008 37*819833afSPeter Tyser #define TEA 0xFF00000C 38*819833afSPeter Tyser #define MMUCR 0xFF000010 39*819833afSPeter Tyser #define PASCR 0xFF000070 40*819833afSPeter Tyser #define IRMCR 0xFF000078 41*819833afSPeter Tyser 42*819833afSPeter Tyser /* CACHE */ 43*819833afSPeter Tyser #define CCR 0xFF00001C 44*819833afSPeter Tyser #define RAMCR 0xFF000074 45*819833afSPeter Tyser 46*819833afSPeter Tyser /* INTC */ 47*819833afSPeter Tyser 48*819833afSPeter Tyser /* BSC */ 49*819833afSPeter Tyser #define CMNCR 0xFEC10000 50*819833afSPeter Tyser #define CS0BCR 0xFEC10004 51*819833afSPeter Tyser #define CS2BCR 0xFEC10008 52*819833afSPeter Tyser #define CS4BCR 0xFEC10010 53*819833afSPeter Tyser #define CS5ABCR 0xFEC10014 54*819833afSPeter Tyser #define CS5BBCR 0xFEC10018 55*819833afSPeter Tyser #define CS6ABCR 0xFEC1001C 56*819833afSPeter Tyser #define CS6BBCR 0xFEC10020 57*819833afSPeter Tyser #define CS0WCR 0xFEC10024 58*819833afSPeter Tyser #define CS2WCR 0xFEC10028 59*819833afSPeter Tyser #define CS4WCR 0xFEC10030 60*819833afSPeter Tyser #define CS5AWCR 0xFEC10034 61*819833afSPeter Tyser #define CS5BWCR 0xFEC10038 62*819833afSPeter Tyser #define CS6AWCR 0xFEC1003C 63*819833afSPeter Tyser #define CS6BWCR 0xFEC10040 64*819833afSPeter Tyser #define RBWTCNT 0xFEC10054 65*819833afSPeter Tyser 66*819833afSPeter Tyser /* SBSC */ 67*819833afSPeter Tyser #define SBSC_SDCR 0xFE400008 68*819833afSPeter Tyser #define SBSC_SDWCR 0xFE40000C 69*819833afSPeter Tyser #define SBSC_SDPCR 0xFE400010 70*819833afSPeter Tyser #define SBSC_RTCSR 0xFE400014 71*819833afSPeter Tyser #define SBSC_RTCNT 0xFE400018 72*819833afSPeter Tyser #define SBSC_RTCOR 0xFE40001C 73*819833afSPeter Tyser #define SBSC_RFCR 0xFE400020 74*819833afSPeter Tyser 75*819833afSPeter Tyser /* DMAC */ 76*819833afSPeter Tyser 77*819833afSPeter Tyser /* CPG */ 78*819833afSPeter Tyser #define FRQCR 0xA4150000 79*819833afSPeter Tyser #define VCLKCR 0xA4150004 80*819833afSPeter Tyser #define SCLKACR 0xA4150008 81*819833afSPeter Tyser #define SCLKBCR 0xA415000C 82*819833afSPeter Tyser #define IRDACLKCR 0xA4150018 83*819833afSPeter Tyser #define PLLCR 0xA4150024 84*819833afSPeter Tyser #define DLLFRQ 0xA4150050 85*819833afSPeter Tyser 86*819833afSPeter Tyser /* LOW POWER MODE */ 87*819833afSPeter Tyser #define STBCR 0xA4150020 88*819833afSPeter Tyser #define MSTPCR0 0xA4150030 89*819833afSPeter Tyser #define MSTPCR1 0xA4150034 90*819833afSPeter Tyser #define MSTPCR2 0xA4150038 91*819833afSPeter Tyser 92*819833afSPeter Tyser /* RWDT */ 93*819833afSPeter Tyser #define RWTCNT 0xA4520000 94*819833afSPeter Tyser #define RWTCSR 0xA4520004 95*819833afSPeter Tyser #define WTCNT RWTCNT 96*819833afSPeter Tyser 97*819833afSPeter Tyser /* TMU */ 98*819833afSPeter Tyser #define TSTR 0xFFD80004 99*819833afSPeter Tyser #define TCOR0 0xFFD80008 100*819833afSPeter Tyser #define TCNT0 0xFFD8000C 101*819833afSPeter Tyser #define TCR0 0xFFD80010 102*819833afSPeter Tyser #define TCOR1 0xFFD80014 103*819833afSPeter Tyser #define TCNT1 0xFFD80018 104*819833afSPeter Tyser #define TCR1 0xFFD8001C 105*819833afSPeter Tyser #define TCOR2 0xFFD80020 106*819833afSPeter Tyser #define TCNT2 0xFFD80024 107*819833afSPeter Tyser #define TCR2 0xFFD80028 108*819833afSPeter Tyser 109*819833afSPeter Tyser /* TPU */ 110*819833afSPeter Tyser 111*819833afSPeter Tyser /* CMT */ 112*819833afSPeter Tyser #define CMSTR 0xA44A0000 113*819833afSPeter Tyser #define CMCSR 0xA44A0060 114*819833afSPeter Tyser #define CMCNT 0xA44A0064 115*819833afSPeter Tyser #define CMCOR 0xA44A0068 116*819833afSPeter Tyser 117*819833afSPeter Tyser /* MSIOF */ 118*819833afSPeter Tyser 119*819833afSPeter Tyser /* SCIF */ 120*819833afSPeter Tyser #define SCIF0_BASE 0xFFE00000 121*819833afSPeter Tyser #define SCIF1_BASE 0xFFE10000 122*819833afSPeter Tyser #define SCIF2_BASE 0xFFE20000 123*819833afSPeter Tyser #define SCIF3_BASE 0xa4e30000 124*819833afSPeter Tyser #define SCIF4_BASE 0xa4e40000 125*819833afSPeter Tyser #define SCIF5_BASE 0xa4e50000 126*819833afSPeter Tyser 127*819833afSPeter Tyser /* RTC */ 128*819833afSPeter Tyser /* IrDA */ 129*819833afSPeter Tyser /* KEYSC */ 130*819833afSPeter Tyser /* USB */ 131*819833afSPeter Tyser /* IIC */ 132*819833afSPeter Tyser /* FLCTL */ 133*819833afSPeter Tyser /* VPU */ 134*819833afSPeter Tyser /* VIO(CEU) */ 135*819833afSPeter Tyser /* VIO(VEU) */ 136*819833afSPeter Tyser /* VIO(BEU) */ 137*819833afSPeter Tyser /* 2DG */ 138*819833afSPeter Tyser /* LCDC */ 139*819833afSPeter Tyser /* VOU */ 140*819833afSPeter Tyser /* TSIF */ 141*819833afSPeter Tyser /* SIU */ 142*819833afSPeter Tyser /* ATAPI */ 143*819833afSPeter Tyser 144*819833afSPeter Tyser /* PFC */ 145*819833afSPeter Tyser #define PACR 0xA4050100 146*819833afSPeter Tyser #define PBCR 0xA4050102 147*819833afSPeter Tyser #define PCCR 0xA4050104 148*819833afSPeter Tyser #define PDCR 0xA4050106 149*819833afSPeter Tyser #define PECR 0xA4050108 150*819833afSPeter Tyser #define PFCR 0xA405010A 151*819833afSPeter Tyser #define PGCR 0xA405010C 152*819833afSPeter Tyser #define PHCR 0xA405010E 153*819833afSPeter Tyser #define PJCR 0xA4050110 154*819833afSPeter Tyser #define PKCR 0xA4050112 155*819833afSPeter Tyser #define PLCR 0xA4050114 156*819833afSPeter Tyser #define PMCR 0xA4050116 157*819833afSPeter Tyser #define PNCR 0xA4050118 158*819833afSPeter Tyser #define PQCR 0xA405011A 159*819833afSPeter Tyser #define PRCR 0xA405011C 160*819833afSPeter Tyser #define PSCR 0xA405011E 161*819833afSPeter Tyser #define PTCR 0xA4050140 162*819833afSPeter Tyser #define PUCR 0xA4050142 163*819833afSPeter Tyser #define PVCR 0xA4050144 164*819833afSPeter Tyser #define PWCR 0xA4050146 165*819833afSPeter Tyser #define PXCR 0xA4050148 166*819833afSPeter Tyser #define PYCR 0xA405014A 167*819833afSPeter Tyser #define PZCR 0xA405014C 168*819833afSPeter Tyser #define PSELA 0xA405014E 169*819833afSPeter Tyser #define PSELB 0xA4050150 170*819833afSPeter Tyser #define PSELC 0xA4050152 171*819833afSPeter Tyser #define PSELD 0xA4050154 172*819833afSPeter Tyser #define HIZCRA 0xA4050158 173*819833afSPeter Tyser #define HIZCRB 0xA405015A 174*819833afSPeter Tyser #define HIZCRC 0xA405015C 175*819833afSPeter Tyser #define HIZCRD 0xA405015E 176*819833afSPeter Tyser #define MSELCRA 0xA4050180 177*819833afSPeter Tyser #define MSELCRB 0xA4050182 178*819833afSPeter Tyser #define PULCR 0xA4050184 179*819833afSPeter Tyser #define DRVCRA 0xA405018A 180*819833afSPeter Tyser #define DRVCRB 0xA405018C 181*819833afSPeter Tyser 182*819833afSPeter Tyser /* I/O Port */ 183*819833afSPeter Tyser #define PADR 0xA4050120 184*819833afSPeter Tyser #define PBDR 0xA4050122 185*819833afSPeter Tyser #define PCDR 0xA4050124 186*819833afSPeter Tyser #define PDDR 0xA4050126 187*819833afSPeter Tyser #define PEDR 0xA4050128 188*819833afSPeter Tyser #define PFDR 0xA405012A 189*819833afSPeter Tyser #define PGDR 0xA405012C 190*819833afSPeter Tyser #define PHDR 0xA405012E 191*819833afSPeter Tyser #define PJDR 0xA4050130 192*819833afSPeter Tyser #define PKDR 0xA4050132 193*819833afSPeter Tyser #define PLDR 0xA4050134 194*819833afSPeter Tyser #define PMDR 0xA4050136 195*819833afSPeter Tyser #define PNDR 0xA4050138 196*819833afSPeter Tyser #define PQDR 0xA405013A 197*819833afSPeter Tyser #define PRDR 0xA405013C 198*819833afSPeter Tyser #define PSDR 0xA405013E 199*819833afSPeter Tyser #define PTDR 0xA4050160 200*819833afSPeter Tyser #define PUDR 0xA4050162 201*819833afSPeter Tyser #define PVDR 0xA4050164 202*819833afSPeter Tyser #define PWDR 0xA4050166 203*819833afSPeter Tyser #define PYDR 0xA4050168 204*819833afSPeter Tyser #define PZDR 0xA405016A 205*819833afSPeter Tyser 206*819833afSPeter Tyser /* UBC */ 207*819833afSPeter Tyser /* H-UDI */ 208*819833afSPeter Tyser 209*819833afSPeter Tyser #endif /* _ASM_CPU_SH7723_H_ */ 210