1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 4 * 5 * SH7722 Internal I/O register 6 */ 7 8 #ifndef _ASM_CPU_SH7722_H_ 9 #define _ASM_CPU_SH7722_H_ 10 11 #define CACHE_OC_NUM_WAYS 4 12 #define CCR_CACHE_INIT 0x0000090d 13 14 /* EXP */ 15 #define TRA 0xFF000020 16 #define EXPEVT 0xFF000024 17 #define INTEVT 0xFF000028 18 19 /* MMU */ 20 #define PTEH 0xFF000000 21 #define PTEL 0xFF000004 22 #define TTB 0xFF000008 23 #define TEA 0xFF00000C 24 #define MMUCR 0xFF000010 25 #define PASCR 0xFF000070 26 #define IRMCR 0xFF000078 27 28 /* CACHE */ 29 #define CCR 0xFF00001C 30 #define RAMCR 0xFF000074 31 32 /* XY MEMORY */ 33 #define XSA 0xFF000050 34 #define YSA 0xFF000054 35 #define XDA 0xFF000058 36 #define YDA 0xFF00005C 37 #define XPR 0xFF000060 38 #define YPR 0xFF000064 39 #define XEA 0xFF000068 40 #define YEA 0xFF00006C 41 42 /* INTC */ 43 #define ICR0 0xA4140000 44 #define ICR1 0xA414001C 45 #define INTPRI0 0xA4140010 46 #define INTREQ0 0xA4140024 47 #define INTMSK0 0xA4140044 48 #define INTMSKCLR0 0xA4140064 49 #define NMIFCR 0xA41400C0 50 #define USERIMASK 0xA4700000 51 #define IPRA 0xA4080000 52 #define IPRB 0xA4080004 53 #define IPRC 0xA4080008 54 #define IPRD 0xA408000C 55 #define IPRE 0xA4080010 56 #define IPRF 0xA4080014 57 #define IPRG 0xA4080018 58 #define IPRH 0xA408001C 59 #define IPRI 0xA4080020 60 #define IPRJ 0xA4080024 61 #define IPRK 0xA4080028 62 #define IPRL 0xA408002C 63 #define IMR0 0xA4080080 64 #define IMR1 0xA4080084 65 #define IMR2 0xA4080088 66 #define IMR3 0xA408008C 67 #define IMR4 0xA4080090 68 #define IMR5 0xA4080094 69 #define IMR6 0xA4080098 70 #define IMR7 0xA408009C 71 #define IMR8 0xA40800A0 72 #define IMR9 0xA40800A4 73 #define IMR10 0xA40800A8 74 #define IMR11 0xA40800AC 75 #define IMCR0 0xA40800C0 76 #define IMCR1 0xA40800C4 77 #define IMCR2 0xA40800C8 78 #define IMCR3 0xA40800CC 79 #define IMCR4 0xA40800D0 80 #define IMCR5 0xA40800D4 81 #define IMCR6 0xA40800D8 82 #define IMCR7 0xA40800DC 83 #define IMCR8 0xA40800E0 84 #define IMCR9 0xA40800E4 85 #define IMCR10 0xA40800E8 86 #define IMCR11 0xA40800EC 87 #define MFI_IPRA 0xA40B0000 88 #define MFI_IPRB 0xA40B0004 89 #define MFI_IPRC 0xA40B0008 90 #define MFI_IPRD 0xA40B000C 91 #define MFI_IPRE 0xA40B0010 92 #define MFI_IPRF 0xA40B0014 93 #define MFI_IPRG 0xA40B0018 94 #define MFI_IPRH 0xA40B001C 95 #define MFI_IPRI 0xA40B0020 96 #define MFI_IPRJ 0xA40B0024 97 #define MFI_IPRK 0xA40B0028 98 #define MFI_IPRL 0xA40B002C 99 #define MFI_IMR0 0xA40B0080 100 #define MFI_IMR1 0xA40B0084 101 #define MFI_IMR2 0xA40B0088 102 #define MFI_IMR3 0xA40B008C 103 #define MFI_IMR4 0xA40B0090 104 #define MFI_IMR5 0xA40B0094 105 #define MFI_IMR6 0xA40B0098 106 #define MFI_IMR7 0xA40B009C 107 #define MFI_IMR8 0xA40B00A0 108 #define MFI_IMR9 0xA40B00A4 109 #define MFI_IMR10 0xA40B00A8 110 #define MFI_IMR11 0xA40B00AC 111 #define MFI_IMCR0 0xA40B00C0 112 #define MFI_IMCR1 0xA40B00C4 113 #define MFI_IMCR2 0xA40B00C8 114 #define MFI_IMCR3 0xA40B00CC 115 #define MFI_IMCR4 0xA40B00D0 116 #define MFI_IMCR5 0xA40B00D4 117 #define MFI_IMCR6 0xA40B00D8 118 #define MFI_IMCR7 0xA40B00DC 119 #define MFI_IMCR8 0xA40B00E0 120 #define MFI_IMCR9 0xA40B00E4 121 #define MFI_IMCR10 0xA40B00E8 122 #define MFI_IMCR11 0xA40B00EC 123 124 /* BSC */ 125 #define CMNCR 0xFEC10000 126 #define CS0BCR 0xFEC10004 127 #define CS2BCR 0xFEC10008 128 #define CS4BCR 0xFEC10010 129 #define CS5ABCR 0xFEC10014 130 #define CS5BBCR 0xFEC10018 131 #define CS6ABCR 0xFEC1001C 132 #define CS6BBCR 0xFEC10020 133 #define CS0WCR 0xFEC10024 134 #define CS2WCR 0xFEC10028 135 #define CS4WCR 0xFEC10030 136 #define CS5AWCR 0xFEC10034 137 #define CS5BWCR 0xFEC10038 138 #define CS6AWCR 0xFEC1003C 139 #define CS6BWCR 0xFEC10040 140 #define RBWTCNT 0xFEC10054 141 142 /* SBSC */ 143 #define SBSC_SDCR 0xFE400008 144 #define SBSC_SDWCR 0xFE40000C 145 #define SBSC_SDPCR 0xFE400010 146 #define SBSC_RTCSR 0xFE400014 147 #define SBSC_RTCNT 0xFE400018 148 #define SBSC_RTCOR 0xFE40001C 149 #define SBSC_RFCR 0xFE400020 150 151 /* DMAC */ 152 #define SAR_0 0xFE008020 153 #define DAR_0 0xFE008024 154 #define TCR_0 0xFE008028 155 #define CHCR_0 0xFE00802C 156 #define SAR_1 0xFE008030 157 #define DAR_1 0xFE008034 158 #define TCR_1 0xFE008038 159 #define CHCR_1 0xFE00803C 160 #define SAR_2 0xFE008040 161 #define DAR_2 0xFE008044 162 #define TCR_2 0xFE008048 163 #define CHCR_2 0xFE00804C 164 #define SAR_3 0xFE008050 165 #define DAR_3 0xFE008054 166 #define TCR_3 0xFE008058 167 #define CHCR_3 0xFE00805C 168 #define SAR_4 0xFE008070 169 #define DAR_4 0xFE008074 170 #define TCR_4 0xFE008078 171 #define CHCR_4 0xFE00807C 172 #define SAR_5 0xFE008080 173 #define DAR_5 0xFE008084 174 #define TCR_5 0xFE008088 175 #define CHCR_5 0xFE00808C 176 #define SARB_0 0xFE008120 177 #define DARB_0 0xFE008124 178 #define TCRB_0 0xFE008128 179 #define SARB_1 0xFE008130 180 #define DARB_1 0xFE008134 181 #define TCRB_1 0xFE008138 182 #define SARB_2 0xFE008140 183 #define DARB_2 0xFE008144 184 #define TCRB_2 0xFE008148 185 #define SARB_3 0xFE008150 186 #define DARB_3 0xFE008154 187 #define TCRB_3 0xFE008158 188 #define DMAOR 0xFE008060 189 #define DMARS_0 0xFE009000 190 #define DMARS_1 0xFE009004 191 #define DMARS_2 0xFE009008 192 193 /* CPG */ 194 #define FRQCR 0xA4150000 195 #define VCLKCR 0xA4150004 196 #define SCLKACR 0xA4150008 197 #define SCLKBCR 0xA415000C 198 #define PLLCR 0xA4150024 199 #define DLLFRQ 0xA4150050 200 201 /* LOW POWER MODE */ 202 #define STBCR 0xA4150020 203 #define MSTPCR0 0xA4150030 204 #define MSTPCR1 0xA4150034 205 #define MSTPCR2 0xA4150038 206 #define BAR 0xA4150040 207 208 /* RWDT */ 209 #define RWTCNT 0xA4520000 210 #define RWTCSR 0xA4520004 211 #define WTCNT RWTCNT 212 213 214 /* TMU */ 215 #define TMU_BASE 0xFFD80000 216 217 /* TPU */ 218 #define TPU_TSTR 0xA4C90000 219 #define TPU_TCR0 0xA4C90010 220 #define TPU_TMDR0 0xA4C90014 221 #define TPU_TIOR0 0xA4C90018 222 #define TPU_TIER0 0xA4C9001C 223 #define TPU_TSR0 0xA4C90020 224 #define TPU_TCNT0 0xA4C90024 225 #define TPU_TGR0A 0xA4C90028 226 #define TPU_TGR0B 0xA4C9002C 227 #define TPU_TGR0C 0xA4C90030 228 #define TPU_TGR0D 0xA4C90034 229 #define TPU_TCR1 0xA4C90050 230 #define TPU_TMDR1 0xA4C90054 231 #define TPU_TIER1 0xA4C9005C 232 #define TPU_TSR1 0xA4C90060 233 #define TPU_TCNT1 0xA4C90064 234 #define TPU_TGR1A 0xA4C90068 235 #define TPU_TGR1B 0xA4C9006C 236 #define TPU_TGR1C 0xA4C90070 237 #define TPU_TGR1D 0xA4C90074 238 #define TPU_TCR2 0xA4C90090 239 #define TPU_TMDR2 0xA4C90094 240 #define TPU_TIER2 0xA4C9009C 241 #define TPU_TSR2 0xA4C900A0 242 #define TPU_TCNT2 0xA4C900A4 243 #define TPU_TGR2A 0xA4C900A8 244 #define TPU_TGR2B 0xA4C900AC 245 #define TPU_TGR2C 0xA4C900B0 246 #define TPU_TGR2D 0xA4C900B4 247 #define TPU_TCR3 0xA4C900D0 248 #define TPU_TMDR3 0xA4C900D4 249 #define TPU_TIER3 0xA4C900DC 250 #define TPU_TSR3 0xA4C900E0 251 #define TPU_TCNT3 0xA4C900E4 252 #define TPU_TGR3A 0xA4C900E8 253 #define TPU_TGR3B 0xA4C900EC 254 #define TPU_TGR3C 0xA4C900F0 255 #define TPU_TGR3D 0xA4C900F4 256 257 /* CMT */ 258 #define CMSTR 0xA44A0000 259 #define CMCSR 0xA44A0060 260 #define CMCNT 0xA44A0064 261 #define CMCOR 0xA44A0068 262 263 /* SIO */ 264 #define SIOMDR 0xA4500000 265 #define SIOCTR 0xA4500004 266 #define SIOSTBCR0 0xA4500008 267 #define SIOSTBCR1 0xA450000C 268 #define SIOTDR 0xA4500014 269 #define SIORDR 0xA4500018 270 #define SIOSTR 0xA450001C 271 #define SIOIER 0xA4500020 272 #define SIOSCR 0xA4500024 273 274 /* SIOF */ 275 #define SIMDR0 0xA4410000 276 #define SISCR0 0xA4410002 277 #define SITDAR0 0xA4410004 278 #define SIRDAR0 0xA4410006 279 #define SICDAR0 0xA4410008 280 #define SICTR0 0xA441000C 281 #define SIFCTR0 0xA4410010 282 #define SISTR0 0xA4410014 283 #define SIIER0 0xA4410016 284 #define SITDR0 0xA4410020 285 #define SIRDR0 0xA4410024 286 #define SITCR0 0xA4410028 287 #define SIRCR0 0xA441002C 288 #define SPICR0 0xA4410030 289 #define SIMDR1 0xA4420000 290 #define SISCR1 0xA4420002 291 #define SITDAR1 0xA4420004 292 #define SIRDAR1 0xA4420006 293 #define SICDAR1 0xA4420008 294 #define SICTR1 0xA442000C 295 #define SIFCTR1 0xA4420010 296 #define SISTR1 0xA4420014 297 #define SIIER1 0xA4420016 298 #define SITDR1 0xA4420020 299 #define SIRDR1 0xA4420024 300 #define SITCR1 0xA4420028 301 #define SIRCR1 0xA442002C 302 #define SPICR1 0xA4420030 303 304 /* SCIF */ 305 #define SCIF0_BASE 0xFFE00000 306 307 /* SIM */ 308 #define SIM_SCSMR 0xA4490000 309 #define SIM_SCBRR 0xA4490002 310 #define SIM_SCSCR 0xA4490004 311 #define SIM_SCTDR 0xA4490006 312 #define SIM_SCSSR 0xA4490008 313 #define SIM_SCRDR 0xA449000A 314 #define SIM_SCSCMR 0xA449000C 315 #define SIM_SCSC2R 0xA449000E 316 #define SIM_SCWAIT 0xA4490010 317 #define SIM_SCGRD 0xA4490012 318 #define SIM_SCSMPL 0xA4490014 319 #define SIM_SCDMAEN 0xA4490016 320 321 /* IrDA */ 322 #define IRIF_INIT1 0xA45D0012 323 #define IRIF_INIT2 0xA45D0014 324 #define IRIF_RINTCLR 0xA45D0016 325 #define IRIF_TINTCLR 0xA45D0018 326 #define IRIF_SIR0 0xA45D0020 327 #define IRIF_SIR1 0xA45D0022 328 #define IRIF_SIR2 0xA45D0024 329 #define IRIF_SIR3 0xA45D0026 330 #define IRIF_SIR_FRM 0xA45D0028 331 #define IRIF_SIR_EOF 0xA45D002A 332 #define IRIF_SIR_FLG 0xA45D002C 333 #define IRIF_SIR_STS2 0xA45D002E 334 #define IRIF_UART0 0xA45D0030 335 #define IRIF_UART1 0xA45D0032 336 #define IRIF_UART2 0xA45D0034 337 #define IRIF_UART3 0xA45D0036 338 #define IRIF_UART4 0xA45D0038 339 #define IRIF_UART5 0xA45D003A 340 #define IRIF_UART6 0xA45D003C 341 #define IRIF_UART7 0xA45D003E 342 #define IRIF_CRC0 0xA45D0040 343 #define IRIF_CRC1 0xA45D0042 344 #define IRIF_CRC2 0xA45D0044 345 #define IRIF_CRC3 0xA45D0046 346 #define IRIF_CRC4 0xA45D0048 347 348 /* IIC */ 349 #define ICDR0 0xA4470000 350 #define ICCR0 0xA4470004 351 #define ICSR0 0xA4470008 352 #define ICIC0 0xA447000C 353 #define ICCL0 0xA4470010 354 #define ICCH0 0xA4470014 355 #define ICDR1 0xA4750000 356 #define ICCR1 0xA4750004 357 #define ICSR1 0xA4750008 358 #define ICIC1 0xA475000C 359 #define ICCL1 0xA4750010 360 #define ICCH1 0xA4750014 361 362 /* FLCTL */ 363 #define FLCMNCR 0xA4530000 364 #define FLCMDCR 0xA4530004 365 #define FLCMCDR 0xA4530008 366 #define FLADR 0xA453000C 367 #define FLDATAR 0xA4530010 368 #define FLDTCNTR 0xA4530014 369 #define FLINTDMACR 0xA4530018 370 #define FLBSYTMR 0xA453001C 371 #define FLBSYCNT 0xA4530020 372 #define FLDTFIFO 0xA4530024 373 #define FLECFIFO 0xA4530028 374 #define FLTRCR 0xA453002C 375 #define FLADR2 0xA453003C 376 377 /* MFI */ 378 #define MFIIDX 0xA4C10000 379 #define MFIGSR 0xA4C10004 380 #define MFISCR 0xA4C10008 381 #define MFIMCR 0xA4C1000C 382 #define MFIIICR 0xA4C10010 383 #define MFIEICR 0xA4C10014 384 #define MFIADR 0xA4C10018 385 #define MFIDATA 0xA4C1001C 386 #define MFIRCR 0xA4C10020 387 #define MFIINTEVT 0xA4C1002C 388 #define MFIIMASK 0xA4C10030 389 #define MFIBCR 0xA4C10040 390 #define MFIADRW 0xA4C10044 391 #define MFIADRR 0xA4C10048 392 #define MFIDATAW 0xA4C1004C 393 #define MFIDATAR 0xA4C10050 394 #define MFIMCRW 0xA4C10054 395 #define MFIMCRR 0xA4C10058 396 #define MFIDNRW 0xA4C1005C 397 #define MFIDNRR 0xA4C10060 398 #define MFISIZEW 0xA4C10064 399 #define MFISIZER 0xA4C10068 400 #define MFIDEVCR 0xA4C10038 401 #define MFISM4 0xA4C10080 402 403 /* VPU */ 404 #define VP4_CTRL 0xFE900000 405 #define VP4_VOL_CTRL 0xFE900004 406 #define VP4_IMAGE_SIZE 0xFE900008 407 #define VP4_MB_NUM 0xFE90000C 408 #define VP4_DWY_ADDR 0xFE900010 409 #define VP4_DWC_ADDR 0xFE900014 410 #define VP4_D2WY_ADDR 0xFE900018 411 #define VP4_D2WC_ADDR 0xFE90001C 412 #define VP4_DP1_ADDR 0xFE900020 413 #define VP4_DP2_ADDR 0xFE900024 414 #define VP4_STRS_ADDR 0xFE900028 415 #define VP4_STRE_ADDR 0xFE90002C 416 #define VP4_VOP_CTRL 0xFE900030 417 #define VP4_VOP_TIME 0xFE900034 418 #define VP4_263_CTRL 0xFE900038 419 #define VP4_264_CTRL 0xFE90003C 420 #define VP4_VLC_CTRL 0xFE900040 421 #define VP4_ENDIAN 0xFE900044 422 #define VP4_CMD 0xFE900048 423 #define VP4_ME_TH1 0xFE90004C 424 #define VP4_ME_TH2 0xFE900050 425 #define VP4_ME_COSTMB 0xFE900054 426 #define VP4_ME_SKIP 0xFE900058 427 #define VP4_ME_CTRL 0xFE90005C 428 #define VP4_MBRF_CTRL 0xFE900060 429 #define VP4_MC_CTRL 0xFE900064 430 #define VP4_PRED_CTRL 0xFE900068 431 #define VP4_SLC_SIZE 0xFE90006C 432 #define VP4_VOP_MINBIT 0xFE900070 433 #define VP4_MB_MAXBIT 0xFE900074 434 #define VP4_MB_TBIT 0xFE900078 435 #define VP4_RCQNT 0xFE90007C 436 #define VP4_RCRP 0xFE900080 437 #define VP4_RCDJ 0xFE900084 438 #define VP4_RCWQ 0xFE900088 439 #define VP4_FWD_TIME 0xFE900094 440 #define VP4_BWD_TIME 0xFE900098 441 #define VP4_PST_TIME 0xFE90009C 442 #define VP4_ILTFRAME 0xFE9000A0 443 #define VP4_EC_REF 0xFE9000A4 444 #define VP4_STATUS 0xFE900100 445 #define VP4_IRQ_ENB 0xFE900104 446 #define VP4_IRQ_STA 0xFE900108 447 #define VP4_VOP_BIT 0xFE90010C 448 #define VP4_PRV_BIT 0xFE900110 449 #define VP4_SLC_MB 0xFE900114 450 #define VP4_QSUM 0xFE900118 451 #define VP4_DEC_ERR 0xFE90011C 452 #define VP4_ERR_AREA 0xFE900120 453 #define VP4_NEXT_CODE 0xFE900124 454 #define VP4_MB_ATTR 0xFE900128 455 #define VP4_DBMON 0xFE90012C 456 #define VP4_DEBUG 0xFE900130 457 #define VP4_ERR_DET 0xFE900134 458 #define VP4_CLK_STOP 0xFE900138 459 #define VP4_MB_SADA 0xFE90013C 460 #define VP4_MB_SADR 0xFE900140 461 #define VP4_MAT_RAM 0xFE901000 462 #define VP4_NC_RAM 0xFE902000 463 #define WT 0xFE9020CC 464 #define VP4_CPY_ADDR 0xFE902264 465 #define VP4_CPC_ADDR 0xFE902268 466 #define VP4_R0Y_ADDR 0xFE90226C 467 #define VP4_R0C_ADDR 0xFE902270 468 #define VP4_R1Y_ADDR 0xFE902274 469 #define VP4_R1C_ADDR 0xFE902278 470 #define VP4_R2Y_ADDR 0xFE90227C 471 #define VP4_R2C_ADDR 0xFE902280 472 #define VP4_R3Y_ADDR 0xFE902284 473 #define VP4_R3C_ADDR 0xFE902288 474 #define VP4_R4Y_ADDR 0xFE90228C 475 #define VP4_R4C_ADDR 0xFE902290 476 #define VP4_R5Y_ADDR 0xFE902294 477 #define VP4_R5C_ADDR 0xFE902298 478 #define VP4_R6Y_ADDR 0xFE90229C 479 #define VP4_R6C_ADDR 0xFE9022A0 480 #define VP4_R7Y_ADDR 0xFE9022A4 481 #define VP4_R7C_ADDR 0xFE9022A8 482 #define VP4_R8Y_ADDR 0xFE9022AC 483 #define VP4_R8C_ADDR 0xFE9022B0 484 #define VP4_R9Y_ADDR 0xFE9022B4 485 #define VP4_R9C_ADDR 0xFE9022B8 486 #define VP4_RAY_ADDR 0xFE9022BC 487 #define VP4_RAC_ADDR 0xFE9022C0 488 #define VP4_RBY_ADDR 0xFE9022C4 489 #define VP4_RBC_ADDR 0xFE9022C8 490 #define VP4_RCY_ADDR 0xFE9022CC 491 #define VP4_RCC_ADDR 0xFE9022D0 492 #define VP4_RDY_ADDR 0xFE9022D4 493 #define VP4_RDC_ADDR 0xFE9022D8 494 #define VP4_REY_ADDR 0xFE9022DC 495 #define VP4_REC_ADDR 0xFE9022E0 496 #define VP4_RFY_ADDR 0xFE9022E4 497 #define VP4_RFC_ADDR 0xFE9022E8 498 499 /* VIO(CEU) */ 500 #define CAPSR 0xFE910000 501 #define CAPCR 0xFE910004 502 #define CAMCR 0xFE910008 503 #define CMCYR 0xFE91000C 504 #define CAMOR 0xFE910010 505 #define CAPWR 0xFE910014 506 #define CAIFR 0xFE910018 507 #define CSTCR 0xFE910020 508 #define CSECR 0xFE910024 509 #define CRCNTR 0xFE910028 510 #define CRCMPR 0xFE91002C 511 #define CFLCR 0xFE910030 512 #define CFSZR 0xFE910034 513 #define CDWDR 0xFE910038 514 #define CDAYR 0xFE91003C 515 #define CDACR 0xFE910040 516 #define CDBYR 0xFE910044 517 #define CDBCR 0xFE910048 518 #define CBDSR 0xFE91004C 519 #define CLFCR 0xFE910060 520 #define CDOCR 0xFE910064 521 #define CDDCR 0xFE910068 522 #define CDDAR 0xFE91006C 523 #define CEIER 0xFE910070 524 #define CETCR 0xFE910074 525 #define CSTSR 0xFE91007C 526 #define CSRTR 0xFE910080 527 #define CDAYR2 0xFE910090 528 #define CDACR2 0xFE910094 529 #define CDBYR2 0xFE910098 530 #define CDBCR2 0xFE91009C 531 532 /* VIO(VEU) */ 533 #define VESTR 0xFE920000 534 #define VESWR 0xFE920010 535 #define VESSR 0xFE920014 536 #define VSAYR 0xFE920018 537 #define VSACR 0xFE92001C 538 #define VBSSR 0xFE920020 539 #define VEDWR 0xFE920030 540 #define VDAYR 0xFE920034 541 #define VDACR 0xFE920038 542 #define VTRCR 0xFE920050 543 #define VRFCR 0xFE920054 544 #define VRFSR 0xFE920058 545 #define VENHR 0xFE92005C 546 #define VFMCR 0xFE920070 547 #define VVTCR 0xFE920074 548 #define VHTCR 0xFE920078 549 #define VAPCR 0xFE920080 550 #define VECCR 0xFE920084 551 #define VAFXR 0xFE920090 552 #define VSWPR 0xFE920094 553 #define VEIER 0xFE9200A0 554 #define VEVTR 0xFE9200A4 555 #define VSTAR 0xFE9200B0 556 #define VBSRR 0xFE9200B4 557 558 /* VIO(BEU) */ 559 #define BESTR 0xFE930000 560 #define BSMWR1 0xFE930010 561 #define BSSZR1 0xFE930014 562 #define BSAYR1 0xFE930018 563 #define BSACR1 0xFE93001C 564 #define BSAAR1 0xFE930020 565 #define BSIFR1 0xFE930024 566 #define BSMWR2 0xFE930028 567 #define BSSZR2 0xFE93002C 568 #define BSAYR2 0xFE930030 569 #define BSACR2 0xFE930034 570 #define BSAAR2 0xFE930038 571 #define BSIFR2 0xFE93003C 572 #define BSMWR3 0xFE930040 573 #define BSSZR3 0xFE930044 574 #define BSAYR3 0xFE930048 575 #define BSACR3 0xFE93004C 576 #define BSAAR3 0xFE930050 577 #define BSIFR3 0xFE930054 578 #define BTPSR 0xFE930058 579 #define BMSMWR1 0xFE930070 580 #define BMSSZR1 0xFE930074 581 #define BMSAYR1 0xFE930078 582 #define BMSACR1 0xFE93007C 583 #define BMSMWR2 0xFE930080 584 #define BMSSZR2 0xFE930084 585 #define BMSAYR2 0xFE930088 586 #define BMSACR2 0xFE93008C 587 #define BMSMWR3 0xFE930090 588 #define BMSSZR3 0xFE930094 589 #define BMSAYR3 0xFE930098 590 #define BMSACR3 0xFE93009C 591 #define BMSMWR4 0xFE9300A0 592 #define BMSSZR4 0xFE9300A4 593 #define BMSAYR4 0xFE9300A8 594 #define BMSACR4 0xFE9300AC 595 #define BMSIFR 0xFE9300F0 596 #define BBLCR0 0xFE930100 597 #define BBLCR1 0xFE930104 598 #define BPROCR 0xFE930108 599 #define BMWCR0 0xFE93010C 600 #define BLOCR1 0xFE930114 601 #define BLOCR2 0xFE930118 602 #define BLOCR3 0xFE93011C 603 #define BMLOCR1 0xFE930120 604 #define BMLOCR2 0xFE930124 605 #define BMLOCR3 0xFE930128 606 #define BMLOCR4 0xFE93012C 607 #define BMPCCR1 0xFE930130 608 #define BMPCCR2 0xFE930134 609 #define BPKFR 0xFE930140 610 #define BPCCR0 0xFE930144 611 #define BPCCR11 0xFE930148 612 #define BPCCR12 0xFE93014C 613 #define BPCCR21 0xFE930150 614 #define BPCCR22 0xFE930154 615 #define BPCCR31 0xFE930158 616 #define BPCCR32 0xFE93015C 617 #define BDMWR 0xFE930160 618 #define BDAYR 0xFE930164 619 #define BDACR 0xFE930168 620 #define BAFXR 0xFE930180 621 #define BSWPR 0xFE930184 622 #define BEIER 0xFE930188 623 #define BEVTR 0xFE93018C 624 #define BRCNTR 0xFE930194 625 #define BSTAR 0xFE930198 626 #define BBRSTR 0xFE93019C 627 #define BRCHR 0xFE9301A0 628 #define CLUT 0xFE933000 629 630 /* JPU */ 631 #define JCMOD 0xFEA00000 632 #define JCCMD 0xFEA00004 633 #define JCSTS 0xFEA00008 634 #define JCQTN 0xFEA0000C 635 #define JCHTN 0xFEA00010 636 #define JCDRIU 0xFEA00014 637 #define JCDRID 0xFEA00018 638 #define JCVSZU 0xFEA0001C 639 #define JCVSZD 0xFEA00020 640 #define JCHSZU 0xFEA00024 641 #define JCHSZD 0xFEA00028 642 #define JCDTCU 0xFEA0002C 643 #define JCDTCM 0xFEA00030 644 #define JCDTCD 0xFEA00034 645 #define JINTE 0xFEA00038 646 #define JINTS 0xFEA0003C 647 #define JCDERR 0xFEA00040 648 #define JCRST 0xFEA00044 649 #define JIFCNT 0xFEA00060 650 #define JIFECNT 0xFEA00070 651 #define JIFESYA1 0xFEA00074 652 #define JIFESCA1 0xFEA00078 653 #define JIFESYA2 0xFEA0007C 654 #define JIFESCA2 0xFEA00080 655 #define JIFESMW 0xFEA00084 656 #define JIFESVSZ 0xFEA00088 657 #define JIFESHSZ 0xFEA0008C 658 #define JIFEDA1 0xFEA00090 659 #define JIFEDA2 0xFEA00094 660 #define JIFEDRSZ 0xFEA00098 661 #define JIFDCNT 0xFEA000A0 662 #define JIFDSA1 0xFEA000A4 663 #define JIFDSA2 0xFEA000A8 664 #define JIFDDRSZ 0xFEA000AC 665 #define JIFDDMW 0xFEA000B0 666 #define JIFDDVSZ 0xFEA000B4 667 #define JIFDDHSZ 0xFEA000B8 668 #define JIFDDYA1 0xFEA000BC 669 #define JIFDDCA1 0xFEA000C0 670 #define JIFDDYA2 0xFEA000C4 671 #define JIFDDCA2 0xFEA000C8 672 #define JCQTBL0 0xFEA10000 673 #define JCQTBL1 0xFEA10040 674 #define JCQTBL2 0xFEA10080 675 #define JCQTBL3 0xFEA100C0 676 #define JCHTBD0 0xFEA10100 677 #define JCHTBA0 0xFEA10120 678 #define JCHTBD1 0xFEA10200 679 #define JCHTBA1 0xFEA10220 680 681 /* LCDC */ 682 #define MLDDCKPAT1R 0xFE940400 683 #define MLDDCKPAT2R 0xFE940404 684 #define SLDDCKPAT1R 0xFE940408 685 #define SLDDCKPAT2R 0xFE94040C 686 #define LDDCKR 0xFE940410 687 #define LDDCKSTPR 0xFE940414 688 #define MLDMT1R 0xFE940418 689 #define MLDMT2R 0xFE94041C 690 #define MLDMT3R 0xFE940420 691 #define MLDDFR 0xFE940424 692 #define MLDSM1R 0xFE940428 693 #define MLDSM2R 0xFE94042C 694 #define MLDSA1R 0xFE940430 695 #define MLDSA2R 0xFE940434 696 #define MLDMLSR 0xFE940438 697 #define MLDWBFR 0xFE94043C 698 #define MLDWBCNTR 0xFE940440 699 #define MLDWBAR 0xFE940444 700 #define MLDHCNR 0xFE940448 701 #define MLDHSYNR 0xFE94044C 702 #define MLDVLNR 0xFE940450 703 #define MLDVSYNR 0xFE940454 704 #define MLDHPDR 0xFE940458 705 #define MLDVPDR 0xFE94045C 706 #define MLDPMR 0xFE940460 707 #define LDPALCR 0xFE940464 708 #define LDINTR 0xFE940468 709 #define LDSR 0xFE94046C 710 #define LDCNT1R 0xFE940470 711 #define LDCNT2R 0xFE940474 712 #define LDRCNTR 0xFE940478 713 #define LDDDSR 0xFE94047C 714 #define LDRCR 0xFE940484 715 #define LDCMRKRGBR 0xFE9404C4 716 #define LDCMRKCMYR 0xFE9404C8 717 #define LDCMRK1R 0xFE9404CC 718 #define LDCMRK2R 0xFE9404D0 719 #define LDCMGKRGBR 0xFE9404D4 720 #define LDCMGKCMYR 0xFE9404D8 721 #define LDCMGK1R 0xFE9404DC 722 #define LDCMGK2R 0xFE9404E0 723 #define LDCMBKRGBR 0xFE9404E4 724 #define LDCMBKCMYR 0xFE9404E8 725 #define LDCMBK1R 0xFE9404EC 726 #define LDCMBK2R 0xFE9404F0 727 #define LDCMHKPR 0xFE9404F4 728 #define LDCMHKQR 0xFE9404F8 729 #define LDCMSELR 0xFE9404FC 730 #define LDCMTVR 0xFE940500 731 #define LDCMTVSELR 0xFE940504 732 #define LDCMDTHR 0xFE940508 733 #define LDCMCNTR 0xFE94050C 734 #define SLDMT1R 0xFE940600 735 #define SLDMT2R 0xFE940604 736 #define SLDMT3R 0xFE940608 737 #define SLDDFR 0xFE94060C 738 #define SLDSM1R 0xFE940610 739 #define SLDSM2R 0xFE940614 740 #define SLDSA1R 0xFE940618 741 #define SLDSA2R 0xFE94061C 742 #define SLDMLSR 0xFE940620 743 #define SLDHCNR 0xFE940624 744 #define SLDHSYNR 0xFE940628 745 #define SLDVLNR 0xFE94062C 746 #define SLDVSYNR 0xFE940630 747 #define SLDHPDR 0xFE940634 748 #define SLDVPDR 0xFE940638 749 #define SLDPMR 0xFE94063C 750 #define LDDWD0R 0xFE940800 751 #define LDDWD1R 0xFE940804 752 #define LDDWD2R 0xFE940808 753 #define LDDWD3R 0xFE94080C 754 #define LDDWD4R 0xFE940810 755 #define LDDWD5R 0xFE940814 756 #define LDDWD6R 0xFE940818 757 #define LDDWD7R 0xFE94081C 758 #define LDDWD8R 0xFE940820 759 #define LDDWD9R 0xFE940824 760 #define LDDWDAR 0xFE940828 761 #define LDDWDBR 0xFE94082C 762 #define LDDWDCR 0xFE940830 763 #define LDDWDDR 0xFE940834 764 #define LDDWDER 0xFE940838 765 #define LDDWDFR 0xFE94083C 766 #define LDDRDR 0xFE940840 767 #define LDDWAR 0xFE940900 768 #define LDDRAR 0xFE940904 769 #define LDPR00 0xFE940000 770 771 /* VOU */ 772 #define VOUER 0xFE960000 773 #define VOUCR 0xFE960004 774 #define VOUSTR 0xFE960008 775 #define VOUVCR 0xFE96000C 776 #define VOUISR 0xFE960010 777 #define VOUBCR 0xFE960014 778 #define VOUDPR 0xFE960018 779 #define VOUDSR 0xFE96001C 780 #define VOUVPR 0xFE960020 781 #define VOUIR 0xFE960024 782 #define VOUSRR 0xFE960028 783 #define VOUMSR 0xFE96002C 784 #define VOUHIR 0xFE960030 785 #define VOUDFR 0xFE960034 786 #define VOUAD1R 0xFE960038 787 #define VOUAD2R 0xFE96003C 788 #define VOUAIR 0xFE960040 789 #define VOUSWR 0xFE960044 790 #define VOURCR 0xFE960048 791 #define VOURPR 0xFE960050 792 793 /* TSIF */ 794 #define TSCTLR 0xA4C80000 795 #define TSPIDR 0xA4C80004 796 #define TSCMDR 0xA4C80008 797 #define TSSTR 0xA4C8000C 798 #define TSTSDR 0xA4C80010 799 #define TSBUFCLRR 0xA4C80014 800 #define TSINTER 0xA4C80018 801 #define TSPSCALER 0xA4C80020 802 #define TSPSCALERR 0xA4C80024 803 #define TSPCRADCMDR 0xA4C80028 804 #define TSPCRADCR 0xA4C8002C 805 #define TSTRPCRADCR 0xA4C80030 806 #define TSDPCRADCR 0xA4C80034 807 808 /* SIU */ 809 #define IFCTL 0xA454C000 810 #define SRCTL 0xA454C004 811 #define SFORM 0xA454C008 812 #define CKCTL 0xA454C00C 813 #define TRDAT 0xA454C010 814 #define STFIFO 0xA454C014 815 #define DPAK 0xA454C01C 816 #define CKREV 0xA454C020 817 #define EVNTC 0xA454C028 818 #define SBCTL 0xA454C040 819 #define SBPSET 0xA454C044 820 #define SBBUS 0xA454C048 821 #define SBWFLG 0xA454C058 822 #define SBRFLG 0xA454C05C 823 #define SBWDAT 0xA454C060 824 #define SBRDAT 0xA454C064 825 #define SBFSTS 0xA454C068 826 #define SBDVCA 0xA454C06C 827 #define SBDVCB 0xA454C070 828 #define SBACTIV 0xA454C074 829 #define DMAIA 0xA454C090 830 #define DMAIB 0xA454C094 831 #define DMAOA 0xA454C098 832 #define DMAOB 0xA454C09C 833 #define SPLRI 0xA454C0B8 834 #define SPRRI 0xA454C0BC 835 #define SPURI 0xA454C0C4 836 #define SPTIS 0xA454C0C8 837 #define SPSTS 0xA454C0CC 838 #define SPCTL 0xA454C0D0 839 #define SPIRI 0xA454C0D4 840 #define SPQCF 0xA454C0D8 841 #define SPQCS 0xA454C0DC 842 #define SPQCT 0xA454C0E0 843 #define DPEAK 0xA454C0F0 844 #define DSLPD 0xA454C0F4 845 #define DSLLV 0xA454C0F8 846 #define BRGASEL 0xA454C100 847 #define BRRA 0xA454C104 848 #define BRGBSEL 0xA454C108 849 #define BRRB 0xA454C10C 850 851 /* USB */ 852 #define IFR0 0xA4480000 853 #define ISR0 0xA4480010 854 #define IER0 0xA4480020 855 #define EPDR0I 0xA4480030 856 #define EPDR0O 0xA4480034 857 #define EPDR0S 0xA4480038 858 #define EPDR1 0xA448003C 859 #define EPDR2 0xA4480040 860 #define EPDR3 0xA4480044 861 #define EPDR4 0xA4480048 862 #define EPDR5 0xA448004C 863 #define EPDR6 0xA4480050 864 #define EPDR7 0xA4480054 865 #define EPDR8 0xA4480058 866 #define EPDR9 0xA448005C 867 #define EPSZ0O 0xA4480080 868 #define EPSZ3 0xA4480084 869 #define EPSZ6 0xA4480088 870 #define EPSZ9 0xA448008C 871 #define TRG 0xA44800A0 872 #define DASTS 0xA44800A4 873 #define FCLR 0xA44800AA 874 #define DMA 0xA44800AC 875 #define EPSTL 0xA44800B2 876 #define CVR 0xA44800B4 877 #define TSR 0xA44800B8 878 #define CTLR 0xA44800BC 879 #define EPIR 0xA44800C0 880 #define XVERCR 0xA44800D0 881 #define STLMR 0xA44800D4 882 883 /* KEYSC */ 884 #define KYCR1 0xA44B0000 885 #define KYCR2 0xA44B0004 886 #define KYINDR 0xA44B0008 887 #define KYOUTDR 0xA44B000C 888 889 /* MMCIF */ 890 #define CMDR0 0xA4448000 891 #define CMDR1 0xA4448001 892 #define CMDR2 0xA4448002 893 #define CMDR3 0xA4448003 894 #define CMDR4 0xA4448004 895 #define CMDR5 0xA4448005 896 #define CMDSTRT 0xA4448006 897 #define OPCR 0xA444800A 898 #define CSTR 0xA444800B 899 #define INTCR0 0xA444800C 900 #define INTCR1 0xA444800D 901 #define INTSTR0 0xA444800E 902 #define INTSTR1 0xA444800F 903 #define CLKON 0xA4448010 904 #define CTOCR 0xA4448011 905 #define VDCNT 0xA4448012 906 #define TBCR 0xA4448014 907 #define MODER 0xA4448016 908 #define CMDTYR 0xA4448018 909 #define RSPTYR 0xA4448019 910 #define TBNCR 0xA444801A 911 #define RSPR0 0xA4448020 912 #define RSPR1 0xA4448021 913 #define RSPR2 0xA4448022 914 #define RSPR3 0xA4448023 915 #define RSPR4 0xA4448024 916 #define RSPR5 0xA4448025 917 #define RSPR6 0xA4448026 918 #define RSPR7 0xA4448027 919 #define RSPR8 0xA4448028 920 #define RSPR9 0xA4448029 921 #define RSPR10 0xA444802A 922 #define RSPR11 0xA444802B 923 #define RSPR12 0xA444802C 924 #define RSPR13 0xA444802D 925 #define RSPR14 0xA444802E 926 #define RSPR15 0xA444802F 927 #define RSPR16 0xA4448030 928 #define RSPRD 0xA4448031 929 #define DTOUTR 0xA4448032 930 #define DR 0xA4448040 931 #define FIFOCLR 0xA4448042 932 #define DMACR 0xA4448044 933 #define INTCR2 0xA4448046 934 #define INTSTR2 0xA4448048 935 936 /* Z3D3 */ 937 #define DLBI 0xFD980000 938 #define DLBD0 0xFD980080 939 #define DLBD1 0xFD980100 940 #define GEWM 0xFD984000 941 #define ICD0 0xFD988000 942 #define ICD1 0xFD989000 943 #define ICT 0xFD98A000 944 #define ILM 0xFD98C000 945 #define FLM0 0xFD98C800 946 #define FLM1 0xFD98D000 947 #define FLUT 0xFD98D800 948 #define Z3D_PC 0xFD98E400 949 #define Z3D_PCSP 0xFD98E404 950 #define Z3D_PAR 0xFD98E408 951 #define Z3D_IMADR 0xFD98E40C 952 #define Z3D_BTR0 0xFD98E410 953 #define Z3D_BTR1 0xFD98E414 954 #define Z3D_BTR2 0xFD98E418 955 #define Z3D_BTR3 0xFD98E41C 956 #define Z3D_LC0 0xFD98E420 957 #define Z3D_LC1 0xFD98E424 958 #define Z3D_LC2 0xFD98E428 959 #define Z3D_LC3 0xFD98E42C 960 #define Z3D_FR0 0xFD98E430 961 #define Z3D_FR1 0xFD98E434 962 #define Z3D_FR2 0xFD98E438 963 #define Z3D_SR 0xFD98E440 964 #define Z3D_SMDR 0xFD98E444 965 #define Z3D_PBIR 0xFD98E448 966 #define Z3D_DMDR 0xFD98E44C 967 #define Z3D_IREG 0xFD98E460 968 #define Z3D_AR00 0xFD98E480 969 #define Z3D_AR01 0xFD98E484 970 #define Z3D_AR02 0xFD98E488 971 #define Z3D_AR03 0xFD98E48C 972 #define Z3D_BR00 0xFD98E490 973 #define Z3D_BR01 0xFD98E494 974 #define Z3D_IXR00 0xFD98E4A0 975 #define Z3D_IXR01 0xFD98E4A4 976 #define Z3D_IXR02 0xFD98E4A8 977 #define Z3D_IXR03 0xFD98E4AC 978 #define Z3D_AR10 0xFD98E4C0 979 #define Z3D_AR11 0xFD98E4C4 980 #define Z3D_AR12 0xFD98E4C8 981 #define Z3D_AR13 0xFD98E4CC 982 #define Z3D_BR10 0xFD98E4D0 983 #define Z3D_BR11 0xFD98E4D4 984 #define Z3D_IXR10 0xFD98E4E0 985 #define Z3D_IXR11 0xFD98E4E4 986 #define Z3D_IXR12 0xFD98E4E8 987 #define Z3D_IXR13 0xFD98E4EC 988 #define Z3D_AR20 0xFD98E500 989 #define Z3D_AR21 0xFD98E504 990 #define Z3D_AR22 0xFD98E508 991 #define Z3D_AR23 0xFD98E50C 992 #define Z3D_BR20 0xFD98E510 993 #define Z3D_BR21 0xFD98E514 994 #define Z3D_IXR20 0xFD98E520 995 #define Z3D_IXR21 0xFD98E524 996 #define Z3D_IXR22 0xFD98E528 997 #define Z3D_IXR23 0xFD98E52C 998 #define Z3D_MR0 0xFD98E540 999 #define Z3D_MR1 0xFD98E544 1000 #define Z3D_MR2 0xFD98E548 1001 #define Z3D_MR3 0xFD98E54C 1002 #define Z3D_WORKRST 0xFD98E558 1003 #define Z3D_WORKWST 0xFD98E55C 1004 #define Z3D_DBADR 0xFD98E560 1005 #define Z3D_DLBPRST 0xFD98E564 1006 #define Z3D_DLBRST 0xFD98E568 1007 #define Z3D_DLBWST 0xFD98E56C 1008 #define Z3D_UDR0 0xFD98E570 1009 #define Z3D_UDR1 0xFD98E574 1010 #define Z3D_UDR2 0xFD98E578 1011 #define Z3D_UDR3 0xFD98E57C 1012 #define Z3D_CCR0 0xFD98E580 1013 #define Z3D_CCR1 0xFD98E584 1014 #define Z3D_EXPR 0xFD98E588 1015 #define Z3D_V0_X 0xFD9A0000 1016 #define Z3D_V0_Y 0xFD9A0004 1017 #define Z3D_V0_Z 0xFD9A0008 1018 #define Z3D_V0_W 0xFD9A000C 1019 #define Z3D_V0_A 0xFD9A0010 1020 #define Z3D_V0_R 0xFD9A0014 1021 #define Z3D_V0_G 0xFD9A0018 1022 #define Z3D_V0_B 0xFD9A001C 1023 #define Z3D_V0_F 0xFD9A0020 1024 #define Z3D_V0_SR 0xFD9A0024 1025 #define Z3D_V0_SG 0xFD9A0028 1026 #define Z3D_V0_SB 0xFD9A002C 1027 #define Z3D_V0_U0 0xFD9A0030 1028 #define Z3D_V0_V0 0xFD9A0034 1029 #define Z3D_V0_U1 0xFD9A0038 1030 #define Z3D_V0_V1 0xFD9A003C 1031 #define Z3D_V1_X 0xFD9A0080 1032 #define Z3D_V1_Y 0xFD9A0084 1033 #define Z3D_V1_Z 0xFD9A0088 1034 #define Z3D_V1_W 0xFD9A008C 1035 #define Z3D_V1_A 0xFD9A0090 1036 #define Z3D_V1_R 0xFD9A0094 1037 #define Z3D_V1_G 0xFD9A0098 1038 #define Z3D_V1_B 0xFD9A009C 1039 #define Z3D_V1_F 0xFD9A00A0 1040 #define Z3D_V1_SR 0xFD9A00A4 1041 #define Z3D_V1_SG 0xFD9A00A8 1042 #define Z3D_V1_SB 0xFD9A00AC 1043 #define Z3D_V1_U0 0xFD9A00B0 1044 #define Z3D_V1_V0 0xFD9A00B4 1045 #define Z3D_V1_U1 0xFD9A00B8 1046 #define Z3D_V1_V1 0xFD9A00BC 1047 #define Z3D_V2_X 0xFD9A0100 1048 #define Z3D_V2_Y 0xFD9A0104 1049 #define Z3D_V2_Z 0xFD9A0108 1050 #define Z3D_V2_W 0xFD9A010C 1051 #define Z3D_V2_A 0xFD9A0110 1052 #define Z3D_V2_R 0xFD9A0114 1053 #define Z3D_V2_G 0xFD9A0118 1054 #define Z3D_V2_B 0xFD9A011C 1055 #define Z3D_V2_F 0xFD9A0120 1056 #define Z3D_V2_SR 0xFD9A0124 1057 #define Z3D_V2_SG 0xFD9A0128 1058 #define Z3D_V2_SB 0xFD9A012C 1059 #define Z3D_V2_U0 0xFD9A0130 1060 #define Z3D_V2_V0 0xFD9A0134 1061 #define Z3D_V2_U1 0xFD9A0138 1062 #define Z3D_V2_V1 0xFD9A013C 1063 #define Z3D_RENDER 0xFD9A0180 1064 #define Z3D_POLYGON_OFFSET 0xFD9A0184 1065 #define Z3D_VERTEX_CONTROL 0xFD9A0200 1066 #define Z3D_STATE_MODE 0xFD9A0204 1067 #define Z3D_FPU_MODE 0xFD9A0318 1068 #define Z3D_SCISSOR_MIN 0xFD9A0400 1069 #define Z3D_SCISSOR_MAX 0xFD9A0404 1070 #define Z3D_TEXTURE_MODE_A 0xFD9A0408 1071 #define Z3D_TEXTURE_MODE_B 0xFD9A040C 1072 #define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 1073 #define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C 1074 #define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 1075 #define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 1076 #define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 1077 #define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C 1078 #define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 1079 #define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 1080 #define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 1081 #define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C 1082 #define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 1083 #define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 1084 #define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 1085 #define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C 1086 #define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 1087 #define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 1088 #define Z3D_TEXTURE_FLUSH 0xFD9A0498 1089 #define Z3D_GAMMA_TABLE0 0xFD9A049C 1090 #define Z3D_GAMMA_TABLE1 0xFD9A04A0 1091 #define Z3D_GAMMA_TABLE2 0xFD9A04A4 1092 #define Z3D_ALPHA_TEST 0xFD9A0800 1093 #define Z3D_STENCIL_TEST 0xFD9A0804 1094 #define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 1095 #define Z3D_MASK 0xFD9A080C 1096 #define Z3D_FBUS_MODE 0xFD9A0810 1097 #define Z3D_GNT_SET 0xFD9A0814 1098 #define Z3D_BETWEEN_TEST 0xFD9A0818 1099 #define Z3D_FB_BASE 0xFD9A081C 1100 #define Z3D_LCD_SIZE 0xFD9A0820 1101 #define Z3D_FB_FLUSH 0xFD9A0824 1102 #define Z3D_CACHE_INVALID 0xFD9A0828 1103 #define Z3D_SC_MODE 0xFD9A0830 1104 #define Z3D_SC0_MIN 0xFD9A0834 1105 #define Z3D_SC0_MAX 0xFD9A0838 1106 #define Z3D_SC1_MIN 0xFD9A083C 1107 #define Z3D_SC1_MAX 0xFD9A0840 1108 #define Z3D_SC2_MIN 0xFD9A0844 1109 #define Z3D_SC2_MAX 0xFD9A0848 1110 #define Z3D_SC3_MIN 0xFD9A084C 1111 #define Z3D_SC3_MAX 0xFD9A0850 1112 #define Z3D_READRESET 0xFD9A0854 1113 #define Z3D_DET_MIN 0xFD9A0858 1114 #define Z3D_DET_MAX 0xFD9A085C 1115 #define Z3D_FB_BASE_SR 0xFD9A0860 1116 #define Z3D_LCD_SIZE_SR 0xFD9A0864 1117 #define Z3D_2D_CTRL_STATUS 0xFD9A0C00 1118 #define Z3D_2D_SIZE 0xFD9A0C04 1119 #define Z3D_2D_SRCLOC 0xFD9A0C08 1120 #define Z3D_2D_DSTLOC 0xFD9A0C0C 1121 #define Z3D_2D_DMAPORT 0xFD9A0C10 1122 #define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 1123 #define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 1124 #define Z3D_2D_STPCOLOR0 0xFD9A0C1C 1125 #define Z3D_2D_STPCOLOR1 0xFD9A0C20 1126 #define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 1127 #define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 1128 #define Z3D_2D_STPPAT_0 0xFD9A0C40 1129 #define Z3D_2D_STPPAT_1 0xFD9A0C44 1130 #define Z3D_2D_STPPAT_2 0xFD9A0C48 1131 #define Z3D_2D_STPPAT_3 0xFD9A0C4C 1132 #define Z3D_2D_STPPAT_4 0xFD9A0C50 1133 #define Z3D_2D_STPPAT_5 0xFD9A0C54 1134 #define Z3D_2D_STPPAT_6 0xFD9A0C58 1135 #define Z3D_2D_STPPAT_7 0xFD9A0C5C 1136 #define Z3D_2D_STPPAT_8 0xFD9A0C60 1137 #define Z3D_2D_STPPAT_9 0xFD9A0C64 1138 #define Z3D_2D_STPPAT_10 0xFD9A0C68 1139 #define Z3D_2D_STPPAT_11 0xFD9A0C6C 1140 #define Z3D_2D_STPPAT_12 0xFD9A0C70 1141 #define Z3D_2D_STPPAT_13 0xFD9A0C74 1142 #define Z3D_2D_STPPAT_14 0xFD9A0C78 1143 #define Z3D_2D_STPPAT_15 0xFD9A0C7C 1144 #define Z3D_2D_STPPAT_16 0xFD9A0C80 1145 #define Z3D_2D_STPPAT_17 0xFD9A0C84 1146 #define Z3D_2D_STPPAT_18 0xFD9A0C88 1147 #define Z3D_2D_STPPAT_19 0xFD9A0C8C 1148 #define Z3D_2D_STPPAT_20 0xFD9A0C90 1149 #define Z3D_2D_STPPAT_21 0xFD9A0C94 1150 #define Z3D_2D_STPPAT_22 0xFD9A0C98 1151 #define Z3D_2D_STPPAT_23 0xFD9A0C9C 1152 #define Z3D_2D_STPPAT_24 0xFD9A0CA0 1153 #define Z3D_2D_STPPAT_25 0xFD9A0CA4 1154 #define Z3D_2D_STPPAT_26 0xFD9A0CA8 1155 #define Z3D_2D_STPPAT_27 0xFD9A0CAC 1156 #define Z3D_2D_STPPAT_28 0xFD9A0CB0 1157 #define Z3D_2D_STPPAT_29 0xFD9A0CB4 1158 #define Z3D_2D_STPPAT_30 0xFD9A0CB8 1159 #define Z3D_2D_STPPAT_31 0xFD9A0CBC 1160 #define Z3D_WR_CTRL 0xFD9A1000 1161 #define Z3D_WR_P0 0xFD9A1004 1162 #define Z3D_WR_P1 0xFD9A1008 1163 #define Z3D_WR_P2 0xFD9A100C 1164 #define Z3D_WR_FGC 0xFD9A1010 1165 #define Z3D_WR_BGC 0xFD9A1014 1166 #define Z3D_WR_SZ 0xFD9A1018 1167 #define Z3D_WR_PATPARAM 0xFD9A101C 1168 #define Z3D_WR_PAT 0xFD9A1020 1169 #define Z3D_SYS_STATUS 0xFD9A1400 1170 #define Z3D_SYS_RESET 0xFD9A1404 1171 #define Z3D_SYS_CLK 0xFD9A1408 1172 #define Z3D_SYS_CONF 0xFD9A140C 1173 #define Z3D_SYS_VERSION 0xFD9A1410 1174 #define Z3D_SYS_DBINV 0xFD9A1418 1175 #define Z3D_SYS_I2F_FMT 0xFD9A1420 1176 #define Z3D_SYS_I2F_SRC 0xFD9A1424 1177 #define Z3D_SYS_I2F_DST 0xFD9A1428 1178 #define Z3D_SYS_GBCNT 0xFD9A1430 1179 #define Z3D_SYS_BSYCNT 0xFD9A1434 1180 #define Z3D_SYS_INT_STATUS 0xFD9A1450 1181 #define Z3D_SYS_INT_MASK 0xFD9A1454 1182 #define Z3D_SYS_INT_CLEAR 0xFD9A1458 1183 #define TCD0 0xFD9C0000 1184 #define TCD1 0xFD9C0400 1185 #define TCD2 0xFD9C0800 1186 #define TCD3 0xFD9C0C00 1187 #define TCT0 0xFD9C1000 1188 #define TCT1 0xFD9C1400 1189 #define TCT2 0xFD9C1800 1190 #define TCT3 0xFD9C1C00 1191 1192 /* PFC */ 1193 #define PACR 0xA4050100 1194 #define PBCR 0xA4050102 1195 #define PCCR 0xA4050104 1196 #define PDCR 0xA4050106 1197 #define PECR 0xA4050108 1198 #define PFCR 0xA405010A 1199 #define PGCR 0xA405010C 1200 #define PHCR 0xA405010E 1201 #define PJCR 0xA4050110 1202 #define PKCR 0xA4050112 1203 #define PLCR 0xA4050114 1204 #define PMCR 0xA4050116 1205 #define PNCR 0xA4050118 1206 #define PQCR 0xA405011A 1207 #define PRCR 0xA405011C 1208 #define PSCR 0xA405011E 1209 #define PTCR 0xA4050140 1210 #define PUCR 0xA4050142 1211 #define PVCR 0xA4050144 1212 #define PWCR 0xA4050146 1213 #define PXCR 0xA4050148 1214 #define PYCR 0xA405014A 1215 #define PZCR 0xA405014C 1216 #define PSELA 0xA405014E 1217 #define PSELB 0xA4050150 1218 #define PSELC 0xA4050152 1219 #define PSELD 0xA4050154 1220 #define PSELE 0xA4050156 1221 #define HIZCRA 0xA4050158 1222 #define HIZCRB 0xA405015A 1223 #define HIZCRC 0xA405015C 1224 #define HIZCRC 0xA405015C 1225 #define MSELCRA 0xA4050180 1226 #define MSELCRB 0xA4050182 1227 #define PULCR 0xA4050184 1228 #define SBSCR 0xA4050186 1229 #define DRVCR 0xA405018A 1230 1231 /* I/O Port */ 1232 #define PADR 0xA4050120 1233 #define PBDR 0xA4050122 1234 #define PCDR 0xA4050124 1235 #define PDDR 0xA4050126 1236 #define PEDR 0xA4050128 1237 #define PFDR 0xA405012A 1238 #define PGDR 0xA405012C 1239 #define PHDR 0xA405012E 1240 #define PJDR 0xA4050130 1241 #define PKDR 0xA4050132 1242 #define PLDR 0xA4050134 1243 #define PMDR 0xA4050136 1244 #define PNDR 0xA4050138 1245 #define PQDR 0xA405013A 1246 #define PRDR 0xA405013C 1247 #define PSDR 0xA405013E 1248 #define PTDR 0xA4050160 1249 #define PUDR 0xA4050162 1250 #define PVDR 0xA4050164 1251 #define PWDR 0xA4050166 1252 #define PXDR 0xA4050168 1253 #define PYDR 0xA405016A 1254 #define PZDR 0xA405016C 1255 1256 /* UBC */ 1257 #define CBR0 0xFF200000 1258 #define CRR0 0xFF200004 1259 #define CAR0 0xFF200008 1260 #define CAMR0 0xFF20000C 1261 #define CBR1 0xFF200020 1262 #define CRR1 0xFF200024 1263 #define CAR1 0xFF200028 1264 #define CAMR1 0xFF20002C 1265 #define CDR1 0xFF200030 1266 #define CDMR1 0xFF200034 1267 #define CETR1 0xFF200038 1268 #define CCMFR 0xFF200600 1269 #define CBCR 0xFF200620 1270 1271 /* H-UDI */ 1272 #define SDIR 0xFC110000 1273 #define SDDRH 0xFC110008 1274 #define SDDRL 0xFC11000A 1275 #define SDINT 0xFC110018 1276 1277 #endif /* _ASM_CPU_SH7722_H_ */ 1278