1 /* 2 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 3 * 4 * SH7722 Internal I/O register 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_CPU_SH7722_H_ 10 #define _ASM_CPU_SH7722_H_ 11 12 #define CACHE_OC_NUM_WAYS 4 13 #define CCR_CACHE_INIT 0x0000090d 14 15 /* EXP */ 16 #define TRA 0xFF000020 17 #define EXPEVT 0xFF000024 18 #define INTEVT 0xFF000028 19 20 /* MMU */ 21 #define PTEH 0xFF000000 22 #define PTEL 0xFF000004 23 #define TTB 0xFF000008 24 #define TEA 0xFF00000C 25 #define MMUCR 0xFF000010 26 #define PASCR 0xFF000070 27 #define IRMCR 0xFF000078 28 29 /* CACHE */ 30 #define CCR 0xFF00001C 31 #define RAMCR 0xFF000074 32 33 /* XY MEMORY */ 34 #define XSA 0xFF000050 35 #define YSA 0xFF000054 36 #define XDA 0xFF000058 37 #define YDA 0xFF00005C 38 #define XPR 0xFF000060 39 #define YPR 0xFF000064 40 #define XEA 0xFF000068 41 #define YEA 0xFF00006C 42 43 /* INTC */ 44 #define ICR0 0xA4140000 45 #define ICR1 0xA414001C 46 #define INTPRI0 0xA4140010 47 #define INTREQ0 0xA4140024 48 #define INTMSK0 0xA4140044 49 #define INTMSKCLR0 0xA4140064 50 #define NMIFCR 0xA41400C0 51 #define USERIMASK 0xA4700000 52 #define IPRA 0xA4080000 53 #define IPRB 0xA4080004 54 #define IPRC 0xA4080008 55 #define IPRD 0xA408000C 56 #define IPRE 0xA4080010 57 #define IPRF 0xA4080014 58 #define IPRG 0xA4080018 59 #define IPRH 0xA408001C 60 #define IPRI 0xA4080020 61 #define IPRJ 0xA4080024 62 #define IPRK 0xA4080028 63 #define IPRL 0xA408002C 64 #define IMR0 0xA4080080 65 #define IMR1 0xA4080084 66 #define IMR2 0xA4080088 67 #define IMR3 0xA408008C 68 #define IMR4 0xA4080090 69 #define IMR5 0xA4080094 70 #define IMR6 0xA4080098 71 #define IMR7 0xA408009C 72 #define IMR8 0xA40800A0 73 #define IMR9 0xA40800A4 74 #define IMR10 0xA40800A8 75 #define IMR11 0xA40800AC 76 #define IMCR0 0xA40800C0 77 #define IMCR1 0xA40800C4 78 #define IMCR2 0xA40800C8 79 #define IMCR3 0xA40800CC 80 #define IMCR4 0xA40800D0 81 #define IMCR5 0xA40800D4 82 #define IMCR6 0xA40800D8 83 #define IMCR7 0xA40800DC 84 #define IMCR8 0xA40800E0 85 #define IMCR9 0xA40800E4 86 #define IMCR10 0xA40800E8 87 #define IMCR11 0xA40800EC 88 #define MFI_IPRA 0xA40B0000 89 #define MFI_IPRB 0xA40B0004 90 #define MFI_IPRC 0xA40B0008 91 #define MFI_IPRD 0xA40B000C 92 #define MFI_IPRE 0xA40B0010 93 #define MFI_IPRF 0xA40B0014 94 #define MFI_IPRG 0xA40B0018 95 #define MFI_IPRH 0xA40B001C 96 #define MFI_IPRI 0xA40B0020 97 #define MFI_IPRJ 0xA40B0024 98 #define MFI_IPRK 0xA40B0028 99 #define MFI_IPRL 0xA40B002C 100 #define MFI_IMR0 0xA40B0080 101 #define MFI_IMR1 0xA40B0084 102 #define MFI_IMR2 0xA40B0088 103 #define MFI_IMR3 0xA40B008C 104 #define MFI_IMR4 0xA40B0090 105 #define MFI_IMR5 0xA40B0094 106 #define MFI_IMR6 0xA40B0098 107 #define MFI_IMR7 0xA40B009C 108 #define MFI_IMR8 0xA40B00A0 109 #define MFI_IMR9 0xA40B00A4 110 #define MFI_IMR10 0xA40B00A8 111 #define MFI_IMR11 0xA40B00AC 112 #define MFI_IMCR0 0xA40B00C0 113 #define MFI_IMCR1 0xA40B00C4 114 #define MFI_IMCR2 0xA40B00C8 115 #define MFI_IMCR3 0xA40B00CC 116 #define MFI_IMCR4 0xA40B00D0 117 #define MFI_IMCR5 0xA40B00D4 118 #define MFI_IMCR6 0xA40B00D8 119 #define MFI_IMCR7 0xA40B00DC 120 #define MFI_IMCR8 0xA40B00E0 121 #define MFI_IMCR9 0xA40B00E4 122 #define MFI_IMCR10 0xA40B00E8 123 #define MFI_IMCR11 0xA40B00EC 124 125 /* BSC */ 126 #define CMNCR 0xFEC10000 127 #define CS0BCR 0xFEC10004 128 #define CS2BCR 0xFEC10008 129 #define CS4BCR 0xFEC10010 130 #define CS5ABCR 0xFEC10014 131 #define CS5BBCR 0xFEC10018 132 #define CS6ABCR 0xFEC1001C 133 #define CS6BBCR 0xFEC10020 134 #define CS0WCR 0xFEC10024 135 #define CS2WCR 0xFEC10028 136 #define CS4WCR 0xFEC10030 137 #define CS5AWCR 0xFEC10034 138 #define CS5BWCR 0xFEC10038 139 #define CS6AWCR 0xFEC1003C 140 #define CS6BWCR 0xFEC10040 141 #define RBWTCNT 0xFEC10054 142 143 /* SBSC */ 144 #define SBSC_SDCR 0xFE400008 145 #define SBSC_SDWCR 0xFE40000C 146 #define SBSC_SDPCR 0xFE400010 147 #define SBSC_RTCSR 0xFE400014 148 #define SBSC_RTCNT 0xFE400018 149 #define SBSC_RTCOR 0xFE40001C 150 #define SBSC_RFCR 0xFE400020 151 152 /* DMAC */ 153 #define SAR_0 0xFE008020 154 #define DAR_0 0xFE008024 155 #define TCR_0 0xFE008028 156 #define CHCR_0 0xFE00802C 157 #define SAR_1 0xFE008030 158 #define DAR_1 0xFE008034 159 #define TCR_1 0xFE008038 160 #define CHCR_1 0xFE00803C 161 #define SAR_2 0xFE008040 162 #define DAR_2 0xFE008044 163 #define TCR_2 0xFE008048 164 #define CHCR_2 0xFE00804C 165 #define SAR_3 0xFE008050 166 #define DAR_3 0xFE008054 167 #define TCR_3 0xFE008058 168 #define CHCR_3 0xFE00805C 169 #define SAR_4 0xFE008070 170 #define DAR_4 0xFE008074 171 #define TCR_4 0xFE008078 172 #define CHCR_4 0xFE00807C 173 #define SAR_5 0xFE008080 174 #define DAR_5 0xFE008084 175 #define TCR_5 0xFE008088 176 #define CHCR_5 0xFE00808C 177 #define SARB_0 0xFE008120 178 #define DARB_0 0xFE008124 179 #define TCRB_0 0xFE008128 180 #define SARB_1 0xFE008130 181 #define DARB_1 0xFE008134 182 #define TCRB_1 0xFE008138 183 #define SARB_2 0xFE008140 184 #define DARB_2 0xFE008144 185 #define TCRB_2 0xFE008148 186 #define SARB_3 0xFE008150 187 #define DARB_3 0xFE008154 188 #define TCRB_3 0xFE008158 189 #define DMAOR 0xFE008060 190 #define DMARS_0 0xFE009000 191 #define DMARS_1 0xFE009004 192 #define DMARS_2 0xFE009008 193 194 /* CPG */ 195 #define FRQCR 0xA4150000 196 #define VCLKCR 0xA4150004 197 #define SCLKACR 0xA4150008 198 #define SCLKBCR 0xA415000C 199 #define PLLCR 0xA4150024 200 #define DLLFRQ 0xA4150050 201 202 /* LOW POWER MODE */ 203 #define STBCR 0xA4150020 204 #define MSTPCR0 0xA4150030 205 #define MSTPCR1 0xA4150034 206 #define MSTPCR2 0xA4150038 207 #define BAR 0xA4150040 208 209 /* RWDT */ 210 #define RWTCNT 0xA4520000 211 #define RWTCSR 0xA4520004 212 #define WTCNT RWTCNT 213 214 215 /* TMU */ 216 #define TMU_BASE 0xFFD80000 217 218 /* TPU */ 219 #define TPU_TSTR 0xA4C90000 220 #define TPU_TCR0 0xA4C90010 221 #define TPU_TMDR0 0xA4C90014 222 #define TPU_TIOR0 0xA4C90018 223 #define TPU_TIER0 0xA4C9001C 224 #define TPU_TSR0 0xA4C90020 225 #define TPU_TCNT0 0xA4C90024 226 #define TPU_TGR0A 0xA4C90028 227 #define TPU_TGR0B 0xA4C9002C 228 #define TPU_TGR0C 0xA4C90030 229 #define TPU_TGR0D 0xA4C90034 230 #define TPU_TCR1 0xA4C90050 231 #define TPU_TMDR1 0xA4C90054 232 #define TPU_TIER1 0xA4C9005C 233 #define TPU_TSR1 0xA4C90060 234 #define TPU_TCNT1 0xA4C90064 235 #define TPU_TGR1A 0xA4C90068 236 #define TPU_TGR1B 0xA4C9006C 237 #define TPU_TGR1C 0xA4C90070 238 #define TPU_TGR1D 0xA4C90074 239 #define TPU_TCR2 0xA4C90090 240 #define TPU_TMDR2 0xA4C90094 241 #define TPU_TIER2 0xA4C9009C 242 #define TPU_TSR2 0xA4C900A0 243 #define TPU_TCNT2 0xA4C900A4 244 #define TPU_TGR2A 0xA4C900A8 245 #define TPU_TGR2B 0xA4C900AC 246 #define TPU_TGR2C 0xA4C900B0 247 #define TPU_TGR2D 0xA4C900B4 248 #define TPU_TCR3 0xA4C900D0 249 #define TPU_TMDR3 0xA4C900D4 250 #define TPU_TIER3 0xA4C900DC 251 #define TPU_TSR3 0xA4C900E0 252 #define TPU_TCNT3 0xA4C900E4 253 #define TPU_TGR3A 0xA4C900E8 254 #define TPU_TGR3B 0xA4C900EC 255 #define TPU_TGR3C 0xA4C900F0 256 #define TPU_TGR3D 0xA4C900F4 257 258 /* CMT */ 259 #define CMSTR 0xA44A0000 260 #define CMCSR 0xA44A0060 261 #define CMCNT 0xA44A0064 262 #define CMCOR 0xA44A0068 263 264 /* SIO */ 265 #define SIOMDR 0xA4500000 266 #define SIOCTR 0xA4500004 267 #define SIOSTBCR0 0xA4500008 268 #define SIOSTBCR1 0xA450000C 269 #define SIOTDR 0xA4500014 270 #define SIORDR 0xA4500018 271 #define SIOSTR 0xA450001C 272 #define SIOIER 0xA4500020 273 #define SIOSCR 0xA4500024 274 275 /* SIOF */ 276 #define SIMDR0 0xA4410000 277 #define SISCR0 0xA4410002 278 #define SITDAR0 0xA4410004 279 #define SIRDAR0 0xA4410006 280 #define SICDAR0 0xA4410008 281 #define SICTR0 0xA441000C 282 #define SIFCTR0 0xA4410010 283 #define SISTR0 0xA4410014 284 #define SIIER0 0xA4410016 285 #define SITDR0 0xA4410020 286 #define SIRDR0 0xA4410024 287 #define SITCR0 0xA4410028 288 #define SIRCR0 0xA441002C 289 #define SPICR0 0xA4410030 290 #define SIMDR1 0xA4420000 291 #define SISCR1 0xA4420002 292 #define SITDAR1 0xA4420004 293 #define SIRDAR1 0xA4420006 294 #define SICDAR1 0xA4420008 295 #define SICTR1 0xA442000C 296 #define SIFCTR1 0xA4420010 297 #define SISTR1 0xA4420014 298 #define SIIER1 0xA4420016 299 #define SITDR1 0xA4420020 300 #define SIRDR1 0xA4420024 301 #define SITCR1 0xA4420028 302 #define SIRCR1 0xA442002C 303 #define SPICR1 0xA4420030 304 305 /* SCIF */ 306 #define SCIF0_BASE 0xFFE00000 307 308 /* SIM */ 309 #define SIM_SCSMR 0xA4490000 310 #define SIM_SCBRR 0xA4490002 311 #define SIM_SCSCR 0xA4490004 312 #define SIM_SCTDR 0xA4490006 313 #define SIM_SCSSR 0xA4490008 314 #define SIM_SCRDR 0xA449000A 315 #define SIM_SCSCMR 0xA449000C 316 #define SIM_SCSC2R 0xA449000E 317 #define SIM_SCWAIT 0xA4490010 318 #define SIM_SCGRD 0xA4490012 319 #define SIM_SCSMPL 0xA4490014 320 #define SIM_SCDMAEN 0xA4490016 321 322 /* IrDA */ 323 #define IRIF_INIT1 0xA45D0012 324 #define IRIF_INIT2 0xA45D0014 325 #define IRIF_RINTCLR 0xA45D0016 326 #define IRIF_TINTCLR 0xA45D0018 327 #define IRIF_SIR0 0xA45D0020 328 #define IRIF_SIR1 0xA45D0022 329 #define IRIF_SIR2 0xA45D0024 330 #define IRIF_SIR3 0xA45D0026 331 #define IRIF_SIR_FRM 0xA45D0028 332 #define IRIF_SIR_EOF 0xA45D002A 333 #define IRIF_SIR_FLG 0xA45D002C 334 #define IRIF_SIR_STS2 0xA45D002E 335 #define IRIF_UART0 0xA45D0030 336 #define IRIF_UART1 0xA45D0032 337 #define IRIF_UART2 0xA45D0034 338 #define IRIF_UART3 0xA45D0036 339 #define IRIF_UART4 0xA45D0038 340 #define IRIF_UART5 0xA45D003A 341 #define IRIF_UART6 0xA45D003C 342 #define IRIF_UART7 0xA45D003E 343 #define IRIF_CRC0 0xA45D0040 344 #define IRIF_CRC1 0xA45D0042 345 #define IRIF_CRC2 0xA45D0044 346 #define IRIF_CRC3 0xA45D0046 347 #define IRIF_CRC4 0xA45D0048 348 349 /* IIC */ 350 #define ICDR0 0xA4470000 351 #define ICCR0 0xA4470004 352 #define ICSR0 0xA4470008 353 #define ICIC0 0xA447000C 354 #define ICCL0 0xA4470010 355 #define ICCH0 0xA4470014 356 #define ICDR1 0xA4750000 357 #define ICCR1 0xA4750004 358 #define ICSR1 0xA4750008 359 #define ICIC1 0xA475000C 360 #define ICCL1 0xA4750010 361 #define ICCH1 0xA4750014 362 363 /* FLCTL */ 364 #define FLCMNCR 0xA4530000 365 #define FLCMDCR 0xA4530004 366 #define FLCMCDR 0xA4530008 367 #define FLADR 0xA453000C 368 #define FLDATAR 0xA4530010 369 #define FLDTCNTR 0xA4530014 370 #define FLINTDMACR 0xA4530018 371 #define FLBSYTMR 0xA453001C 372 #define FLBSYCNT 0xA4530020 373 #define FLDTFIFO 0xA4530024 374 #define FLECFIFO 0xA4530028 375 #define FLTRCR 0xA453002C 376 #define FLADR2 0xA453003C 377 378 /* MFI */ 379 #define MFIIDX 0xA4C10000 380 #define MFIGSR 0xA4C10004 381 #define MFISCR 0xA4C10008 382 #define MFIMCR 0xA4C1000C 383 #define MFIIICR 0xA4C10010 384 #define MFIEICR 0xA4C10014 385 #define MFIADR 0xA4C10018 386 #define MFIDATA 0xA4C1001C 387 #define MFIRCR 0xA4C10020 388 #define MFIINTEVT 0xA4C1002C 389 #define MFIIMASK 0xA4C10030 390 #define MFIBCR 0xA4C10040 391 #define MFIADRW 0xA4C10044 392 #define MFIADRR 0xA4C10048 393 #define MFIDATAW 0xA4C1004C 394 #define MFIDATAR 0xA4C10050 395 #define MFIMCRW 0xA4C10054 396 #define MFIMCRR 0xA4C10058 397 #define MFIDNRW 0xA4C1005C 398 #define MFIDNRR 0xA4C10060 399 #define MFISIZEW 0xA4C10064 400 #define MFISIZER 0xA4C10068 401 #define MFIDEVCR 0xA4C10038 402 #define MFISM4 0xA4C10080 403 404 /* VPU */ 405 #define VP4_CTRL 0xFE900000 406 #define VP4_VOL_CTRL 0xFE900004 407 #define VP4_IMAGE_SIZE 0xFE900008 408 #define VP4_MB_NUM 0xFE90000C 409 #define VP4_DWY_ADDR 0xFE900010 410 #define VP4_DWC_ADDR 0xFE900014 411 #define VP4_D2WY_ADDR 0xFE900018 412 #define VP4_D2WC_ADDR 0xFE90001C 413 #define VP4_DP1_ADDR 0xFE900020 414 #define VP4_DP2_ADDR 0xFE900024 415 #define VP4_STRS_ADDR 0xFE900028 416 #define VP4_STRE_ADDR 0xFE90002C 417 #define VP4_VOP_CTRL 0xFE900030 418 #define VP4_VOP_TIME 0xFE900034 419 #define VP4_263_CTRL 0xFE900038 420 #define VP4_264_CTRL 0xFE90003C 421 #define VP4_VLC_CTRL 0xFE900040 422 #define VP4_ENDIAN 0xFE900044 423 #define VP4_CMD 0xFE900048 424 #define VP4_ME_TH1 0xFE90004C 425 #define VP4_ME_TH2 0xFE900050 426 #define VP4_ME_COSTMB 0xFE900054 427 #define VP4_ME_SKIP 0xFE900058 428 #define VP4_ME_CTRL 0xFE90005C 429 #define VP4_MBRF_CTRL 0xFE900060 430 #define VP4_MC_CTRL 0xFE900064 431 #define VP4_PRED_CTRL 0xFE900068 432 #define VP4_SLC_SIZE 0xFE90006C 433 #define VP4_VOP_MINBIT 0xFE900070 434 #define VP4_MB_MAXBIT 0xFE900074 435 #define VP4_MB_TBIT 0xFE900078 436 #define VP4_RCQNT 0xFE90007C 437 #define VP4_RCRP 0xFE900080 438 #define VP4_RCDJ 0xFE900084 439 #define VP4_RCWQ 0xFE900088 440 #define VP4_FWD_TIME 0xFE900094 441 #define VP4_BWD_TIME 0xFE900098 442 #define VP4_PST_TIME 0xFE90009C 443 #define VP4_ILTFRAME 0xFE9000A0 444 #define VP4_EC_REF 0xFE9000A4 445 #define VP4_STATUS 0xFE900100 446 #define VP4_IRQ_ENB 0xFE900104 447 #define VP4_IRQ_STA 0xFE900108 448 #define VP4_VOP_BIT 0xFE90010C 449 #define VP4_PRV_BIT 0xFE900110 450 #define VP4_SLC_MB 0xFE900114 451 #define VP4_QSUM 0xFE900118 452 #define VP4_DEC_ERR 0xFE90011C 453 #define VP4_ERR_AREA 0xFE900120 454 #define VP4_NEXT_CODE 0xFE900124 455 #define VP4_MB_ATTR 0xFE900128 456 #define VP4_DBMON 0xFE90012C 457 #define VP4_DEBUG 0xFE900130 458 #define VP4_ERR_DET 0xFE900134 459 #define VP4_CLK_STOP 0xFE900138 460 #define VP4_MB_SADA 0xFE90013C 461 #define VP4_MB_SADR 0xFE900140 462 #define VP4_MAT_RAM 0xFE901000 463 #define VP4_NC_RAM 0xFE902000 464 #define WT 0xFE9020CC 465 #define VP4_CPY_ADDR 0xFE902264 466 #define VP4_CPC_ADDR 0xFE902268 467 #define VP4_R0Y_ADDR 0xFE90226C 468 #define VP4_R0C_ADDR 0xFE902270 469 #define VP4_R1Y_ADDR 0xFE902274 470 #define VP4_R1C_ADDR 0xFE902278 471 #define VP4_R2Y_ADDR 0xFE90227C 472 #define VP4_R2C_ADDR 0xFE902280 473 #define VP4_R3Y_ADDR 0xFE902284 474 #define VP4_R3C_ADDR 0xFE902288 475 #define VP4_R4Y_ADDR 0xFE90228C 476 #define VP4_R4C_ADDR 0xFE902290 477 #define VP4_R5Y_ADDR 0xFE902294 478 #define VP4_R5C_ADDR 0xFE902298 479 #define VP4_R6Y_ADDR 0xFE90229C 480 #define VP4_R6C_ADDR 0xFE9022A0 481 #define VP4_R7Y_ADDR 0xFE9022A4 482 #define VP4_R7C_ADDR 0xFE9022A8 483 #define VP4_R8Y_ADDR 0xFE9022AC 484 #define VP4_R8C_ADDR 0xFE9022B0 485 #define VP4_R9Y_ADDR 0xFE9022B4 486 #define VP4_R9C_ADDR 0xFE9022B8 487 #define VP4_RAY_ADDR 0xFE9022BC 488 #define VP4_RAC_ADDR 0xFE9022C0 489 #define VP4_RBY_ADDR 0xFE9022C4 490 #define VP4_RBC_ADDR 0xFE9022C8 491 #define VP4_RCY_ADDR 0xFE9022CC 492 #define VP4_RCC_ADDR 0xFE9022D0 493 #define VP4_RDY_ADDR 0xFE9022D4 494 #define VP4_RDC_ADDR 0xFE9022D8 495 #define VP4_REY_ADDR 0xFE9022DC 496 #define VP4_REC_ADDR 0xFE9022E0 497 #define VP4_RFY_ADDR 0xFE9022E4 498 #define VP4_RFC_ADDR 0xFE9022E8 499 500 /* VIO(CEU) */ 501 #define CAPSR 0xFE910000 502 #define CAPCR 0xFE910004 503 #define CAMCR 0xFE910008 504 #define CMCYR 0xFE91000C 505 #define CAMOR 0xFE910010 506 #define CAPWR 0xFE910014 507 #define CAIFR 0xFE910018 508 #define CSTCR 0xFE910020 509 #define CSECR 0xFE910024 510 #define CRCNTR 0xFE910028 511 #define CRCMPR 0xFE91002C 512 #define CFLCR 0xFE910030 513 #define CFSZR 0xFE910034 514 #define CDWDR 0xFE910038 515 #define CDAYR 0xFE91003C 516 #define CDACR 0xFE910040 517 #define CDBYR 0xFE910044 518 #define CDBCR 0xFE910048 519 #define CBDSR 0xFE91004C 520 #define CLFCR 0xFE910060 521 #define CDOCR 0xFE910064 522 #define CDDCR 0xFE910068 523 #define CDDAR 0xFE91006C 524 #define CEIER 0xFE910070 525 #define CETCR 0xFE910074 526 #define CSTSR 0xFE91007C 527 #define CSRTR 0xFE910080 528 #define CDAYR2 0xFE910090 529 #define CDACR2 0xFE910094 530 #define CDBYR2 0xFE910098 531 #define CDBCR2 0xFE91009C 532 533 /* VIO(VEU) */ 534 #define VESTR 0xFE920000 535 #define VESWR 0xFE920010 536 #define VESSR 0xFE920014 537 #define VSAYR 0xFE920018 538 #define VSACR 0xFE92001C 539 #define VBSSR 0xFE920020 540 #define VEDWR 0xFE920030 541 #define VDAYR 0xFE920034 542 #define VDACR 0xFE920038 543 #define VTRCR 0xFE920050 544 #define VRFCR 0xFE920054 545 #define VRFSR 0xFE920058 546 #define VENHR 0xFE92005C 547 #define VFMCR 0xFE920070 548 #define VVTCR 0xFE920074 549 #define VHTCR 0xFE920078 550 #define VAPCR 0xFE920080 551 #define VECCR 0xFE920084 552 #define VAFXR 0xFE920090 553 #define VSWPR 0xFE920094 554 #define VEIER 0xFE9200A0 555 #define VEVTR 0xFE9200A4 556 #define VSTAR 0xFE9200B0 557 #define VBSRR 0xFE9200B4 558 559 /* VIO(BEU) */ 560 #define BESTR 0xFE930000 561 #define BSMWR1 0xFE930010 562 #define BSSZR1 0xFE930014 563 #define BSAYR1 0xFE930018 564 #define BSACR1 0xFE93001C 565 #define BSAAR1 0xFE930020 566 #define BSIFR1 0xFE930024 567 #define BSMWR2 0xFE930028 568 #define BSSZR2 0xFE93002C 569 #define BSAYR2 0xFE930030 570 #define BSACR2 0xFE930034 571 #define BSAAR2 0xFE930038 572 #define BSIFR2 0xFE93003C 573 #define BSMWR3 0xFE930040 574 #define BSSZR3 0xFE930044 575 #define BSAYR3 0xFE930048 576 #define BSACR3 0xFE93004C 577 #define BSAAR3 0xFE930050 578 #define BSIFR3 0xFE930054 579 #define BTPSR 0xFE930058 580 #define BMSMWR1 0xFE930070 581 #define BMSSZR1 0xFE930074 582 #define BMSAYR1 0xFE930078 583 #define BMSACR1 0xFE93007C 584 #define BMSMWR2 0xFE930080 585 #define BMSSZR2 0xFE930084 586 #define BMSAYR2 0xFE930088 587 #define BMSACR2 0xFE93008C 588 #define BMSMWR3 0xFE930090 589 #define BMSSZR3 0xFE930094 590 #define BMSAYR3 0xFE930098 591 #define BMSACR3 0xFE93009C 592 #define BMSMWR4 0xFE9300A0 593 #define BMSSZR4 0xFE9300A4 594 #define BMSAYR4 0xFE9300A8 595 #define BMSACR4 0xFE9300AC 596 #define BMSIFR 0xFE9300F0 597 #define BBLCR0 0xFE930100 598 #define BBLCR1 0xFE930104 599 #define BPROCR 0xFE930108 600 #define BMWCR0 0xFE93010C 601 #define BLOCR1 0xFE930114 602 #define BLOCR2 0xFE930118 603 #define BLOCR3 0xFE93011C 604 #define BMLOCR1 0xFE930120 605 #define BMLOCR2 0xFE930124 606 #define BMLOCR3 0xFE930128 607 #define BMLOCR4 0xFE93012C 608 #define BMPCCR1 0xFE930130 609 #define BMPCCR2 0xFE930134 610 #define BPKFR 0xFE930140 611 #define BPCCR0 0xFE930144 612 #define BPCCR11 0xFE930148 613 #define BPCCR12 0xFE93014C 614 #define BPCCR21 0xFE930150 615 #define BPCCR22 0xFE930154 616 #define BPCCR31 0xFE930158 617 #define BPCCR32 0xFE93015C 618 #define BDMWR 0xFE930160 619 #define BDAYR 0xFE930164 620 #define BDACR 0xFE930168 621 #define BAFXR 0xFE930180 622 #define BSWPR 0xFE930184 623 #define BEIER 0xFE930188 624 #define BEVTR 0xFE93018C 625 #define BRCNTR 0xFE930194 626 #define BSTAR 0xFE930198 627 #define BBRSTR 0xFE93019C 628 #define BRCHR 0xFE9301A0 629 #define CLUT 0xFE933000 630 631 /* JPU */ 632 #define JCMOD 0xFEA00000 633 #define JCCMD 0xFEA00004 634 #define JCSTS 0xFEA00008 635 #define JCQTN 0xFEA0000C 636 #define JCHTN 0xFEA00010 637 #define JCDRIU 0xFEA00014 638 #define JCDRID 0xFEA00018 639 #define JCVSZU 0xFEA0001C 640 #define JCVSZD 0xFEA00020 641 #define JCHSZU 0xFEA00024 642 #define JCHSZD 0xFEA00028 643 #define JCDTCU 0xFEA0002C 644 #define JCDTCM 0xFEA00030 645 #define JCDTCD 0xFEA00034 646 #define JINTE 0xFEA00038 647 #define JINTS 0xFEA0003C 648 #define JCDERR 0xFEA00040 649 #define JCRST 0xFEA00044 650 #define JIFCNT 0xFEA00060 651 #define JIFECNT 0xFEA00070 652 #define JIFESYA1 0xFEA00074 653 #define JIFESCA1 0xFEA00078 654 #define JIFESYA2 0xFEA0007C 655 #define JIFESCA2 0xFEA00080 656 #define JIFESMW 0xFEA00084 657 #define JIFESVSZ 0xFEA00088 658 #define JIFESHSZ 0xFEA0008C 659 #define JIFEDA1 0xFEA00090 660 #define JIFEDA2 0xFEA00094 661 #define JIFEDRSZ 0xFEA00098 662 #define JIFDCNT 0xFEA000A0 663 #define JIFDSA1 0xFEA000A4 664 #define JIFDSA2 0xFEA000A8 665 #define JIFDDRSZ 0xFEA000AC 666 #define JIFDDMW 0xFEA000B0 667 #define JIFDDVSZ 0xFEA000B4 668 #define JIFDDHSZ 0xFEA000B8 669 #define JIFDDYA1 0xFEA000BC 670 #define JIFDDCA1 0xFEA000C0 671 #define JIFDDYA2 0xFEA000C4 672 #define JIFDDCA2 0xFEA000C8 673 #define JCQTBL0 0xFEA10000 674 #define JCQTBL1 0xFEA10040 675 #define JCQTBL2 0xFEA10080 676 #define JCQTBL3 0xFEA100C0 677 #define JCHTBD0 0xFEA10100 678 #define JCHTBA0 0xFEA10120 679 #define JCHTBD1 0xFEA10200 680 #define JCHTBA1 0xFEA10220 681 682 /* LCDC */ 683 #define MLDDCKPAT1R 0xFE940400 684 #define MLDDCKPAT2R 0xFE940404 685 #define SLDDCKPAT1R 0xFE940408 686 #define SLDDCKPAT2R 0xFE94040C 687 #define LDDCKR 0xFE940410 688 #define LDDCKSTPR 0xFE940414 689 #define MLDMT1R 0xFE940418 690 #define MLDMT2R 0xFE94041C 691 #define MLDMT3R 0xFE940420 692 #define MLDDFR 0xFE940424 693 #define MLDSM1R 0xFE940428 694 #define MLDSM2R 0xFE94042C 695 #define MLDSA1R 0xFE940430 696 #define MLDSA2R 0xFE940434 697 #define MLDMLSR 0xFE940438 698 #define MLDWBFR 0xFE94043C 699 #define MLDWBCNTR 0xFE940440 700 #define MLDWBAR 0xFE940444 701 #define MLDHCNR 0xFE940448 702 #define MLDHSYNR 0xFE94044C 703 #define MLDVLNR 0xFE940450 704 #define MLDVSYNR 0xFE940454 705 #define MLDHPDR 0xFE940458 706 #define MLDVPDR 0xFE94045C 707 #define MLDPMR 0xFE940460 708 #define LDPALCR 0xFE940464 709 #define LDINTR 0xFE940468 710 #define LDSR 0xFE94046C 711 #define LDCNT1R 0xFE940470 712 #define LDCNT2R 0xFE940474 713 #define LDRCNTR 0xFE940478 714 #define LDDDSR 0xFE94047C 715 #define LDRCR 0xFE940484 716 #define LDCMRKRGBR 0xFE9404C4 717 #define LDCMRKCMYR 0xFE9404C8 718 #define LDCMRK1R 0xFE9404CC 719 #define LDCMRK2R 0xFE9404D0 720 #define LDCMGKRGBR 0xFE9404D4 721 #define LDCMGKCMYR 0xFE9404D8 722 #define LDCMGK1R 0xFE9404DC 723 #define LDCMGK2R 0xFE9404E0 724 #define LDCMBKRGBR 0xFE9404E4 725 #define LDCMBKCMYR 0xFE9404E8 726 #define LDCMBK1R 0xFE9404EC 727 #define LDCMBK2R 0xFE9404F0 728 #define LDCMHKPR 0xFE9404F4 729 #define LDCMHKQR 0xFE9404F8 730 #define LDCMSELR 0xFE9404FC 731 #define LDCMTVR 0xFE940500 732 #define LDCMTVSELR 0xFE940504 733 #define LDCMDTHR 0xFE940508 734 #define LDCMCNTR 0xFE94050C 735 #define SLDMT1R 0xFE940600 736 #define SLDMT2R 0xFE940604 737 #define SLDMT3R 0xFE940608 738 #define SLDDFR 0xFE94060C 739 #define SLDSM1R 0xFE940610 740 #define SLDSM2R 0xFE940614 741 #define SLDSA1R 0xFE940618 742 #define SLDSA2R 0xFE94061C 743 #define SLDMLSR 0xFE940620 744 #define SLDHCNR 0xFE940624 745 #define SLDHSYNR 0xFE940628 746 #define SLDVLNR 0xFE94062C 747 #define SLDVSYNR 0xFE940630 748 #define SLDHPDR 0xFE940634 749 #define SLDVPDR 0xFE940638 750 #define SLDPMR 0xFE94063C 751 #define LDDWD0R 0xFE940800 752 #define LDDWD1R 0xFE940804 753 #define LDDWD2R 0xFE940808 754 #define LDDWD3R 0xFE94080C 755 #define LDDWD4R 0xFE940810 756 #define LDDWD5R 0xFE940814 757 #define LDDWD6R 0xFE940818 758 #define LDDWD7R 0xFE94081C 759 #define LDDWD8R 0xFE940820 760 #define LDDWD9R 0xFE940824 761 #define LDDWDAR 0xFE940828 762 #define LDDWDBR 0xFE94082C 763 #define LDDWDCR 0xFE940830 764 #define LDDWDDR 0xFE940834 765 #define LDDWDER 0xFE940838 766 #define LDDWDFR 0xFE94083C 767 #define LDDRDR 0xFE940840 768 #define LDDWAR 0xFE940900 769 #define LDDRAR 0xFE940904 770 #define LDPR00 0xFE940000 771 772 /* VOU */ 773 #define VOUER 0xFE960000 774 #define VOUCR 0xFE960004 775 #define VOUSTR 0xFE960008 776 #define VOUVCR 0xFE96000C 777 #define VOUISR 0xFE960010 778 #define VOUBCR 0xFE960014 779 #define VOUDPR 0xFE960018 780 #define VOUDSR 0xFE96001C 781 #define VOUVPR 0xFE960020 782 #define VOUIR 0xFE960024 783 #define VOUSRR 0xFE960028 784 #define VOUMSR 0xFE96002C 785 #define VOUHIR 0xFE960030 786 #define VOUDFR 0xFE960034 787 #define VOUAD1R 0xFE960038 788 #define VOUAD2R 0xFE96003C 789 #define VOUAIR 0xFE960040 790 #define VOUSWR 0xFE960044 791 #define VOURCR 0xFE960048 792 #define VOURPR 0xFE960050 793 794 /* TSIF */ 795 #define TSCTLR 0xA4C80000 796 #define TSPIDR 0xA4C80004 797 #define TSCMDR 0xA4C80008 798 #define TSSTR 0xA4C8000C 799 #define TSTSDR 0xA4C80010 800 #define TSBUFCLRR 0xA4C80014 801 #define TSINTER 0xA4C80018 802 #define TSPSCALER 0xA4C80020 803 #define TSPSCALERR 0xA4C80024 804 #define TSPCRADCMDR 0xA4C80028 805 #define TSPCRADCR 0xA4C8002C 806 #define TSTRPCRADCR 0xA4C80030 807 #define TSDPCRADCR 0xA4C80034 808 809 /* SIU */ 810 #define IFCTL 0xA454C000 811 #define SRCTL 0xA454C004 812 #define SFORM 0xA454C008 813 #define CKCTL 0xA454C00C 814 #define TRDAT 0xA454C010 815 #define STFIFO 0xA454C014 816 #define DPAK 0xA454C01C 817 #define CKREV 0xA454C020 818 #define EVNTC 0xA454C028 819 #define SBCTL 0xA454C040 820 #define SBPSET 0xA454C044 821 #define SBBUS 0xA454C048 822 #define SBWFLG 0xA454C058 823 #define SBRFLG 0xA454C05C 824 #define SBWDAT 0xA454C060 825 #define SBRDAT 0xA454C064 826 #define SBFSTS 0xA454C068 827 #define SBDVCA 0xA454C06C 828 #define SBDVCB 0xA454C070 829 #define SBACTIV 0xA454C074 830 #define DMAIA 0xA454C090 831 #define DMAIB 0xA454C094 832 #define DMAOA 0xA454C098 833 #define DMAOB 0xA454C09C 834 #define SPLRI 0xA454C0B8 835 #define SPRRI 0xA454C0BC 836 #define SPURI 0xA454C0C4 837 #define SPTIS 0xA454C0C8 838 #define SPSTS 0xA454C0CC 839 #define SPCTL 0xA454C0D0 840 #define SPIRI 0xA454C0D4 841 #define SPQCF 0xA454C0D8 842 #define SPQCS 0xA454C0DC 843 #define SPQCT 0xA454C0E0 844 #define DPEAK 0xA454C0F0 845 #define DSLPD 0xA454C0F4 846 #define DSLLV 0xA454C0F8 847 #define BRGASEL 0xA454C100 848 #define BRRA 0xA454C104 849 #define BRGBSEL 0xA454C108 850 #define BRRB 0xA454C10C 851 852 /* USB */ 853 #define IFR0 0xA4480000 854 #define ISR0 0xA4480010 855 #define IER0 0xA4480020 856 #define EPDR0I 0xA4480030 857 #define EPDR0O 0xA4480034 858 #define EPDR0S 0xA4480038 859 #define EPDR1 0xA448003C 860 #define EPDR2 0xA4480040 861 #define EPDR3 0xA4480044 862 #define EPDR4 0xA4480048 863 #define EPDR5 0xA448004C 864 #define EPDR6 0xA4480050 865 #define EPDR7 0xA4480054 866 #define EPDR8 0xA4480058 867 #define EPDR9 0xA448005C 868 #define EPSZ0O 0xA4480080 869 #define EPSZ3 0xA4480084 870 #define EPSZ6 0xA4480088 871 #define EPSZ9 0xA448008C 872 #define TRG 0xA44800A0 873 #define DASTS 0xA44800A4 874 #define FCLR 0xA44800AA 875 #define DMA 0xA44800AC 876 #define EPSTL 0xA44800B2 877 #define CVR 0xA44800B4 878 #define TSR 0xA44800B8 879 #define CTLR 0xA44800BC 880 #define EPIR 0xA44800C0 881 #define XVERCR 0xA44800D0 882 #define STLMR 0xA44800D4 883 884 /* KEYSC */ 885 #define KYCR1 0xA44B0000 886 #define KYCR2 0xA44B0004 887 #define KYINDR 0xA44B0008 888 #define KYOUTDR 0xA44B000C 889 890 /* MMCIF */ 891 #define CMDR0 0xA4448000 892 #define CMDR1 0xA4448001 893 #define CMDR2 0xA4448002 894 #define CMDR3 0xA4448003 895 #define CMDR4 0xA4448004 896 #define CMDR5 0xA4448005 897 #define CMDSTRT 0xA4448006 898 #define OPCR 0xA444800A 899 #define CSTR 0xA444800B 900 #define INTCR0 0xA444800C 901 #define INTCR1 0xA444800D 902 #define INTSTR0 0xA444800E 903 #define INTSTR1 0xA444800F 904 #define CLKON 0xA4448010 905 #define CTOCR 0xA4448011 906 #define VDCNT 0xA4448012 907 #define TBCR 0xA4448014 908 #define MODER 0xA4448016 909 #define CMDTYR 0xA4448018 910 #define RSPTYR 0xA4448019 911 #define TBNCR 0xA444801A 912 #define RSPR0 0xA4448020 913 #define RSPR1 0xA4448021 914 #define RSPR2 0xA4448022 915 #define RSPR3 0xA4448023 916 #define RSPR4 0xA4448024 917 #define RSPR5 0xA4448025 918 #define RSPR6 0xA4448026 919 #define RSPR7 0xA4448027 920 #define RSPR8 0xA4448028 921 #define RSPR9 0xA4448029 922 #define RSPR10 0xA444802A 923 #define RSPR11 0xA444802B 924 #define RSPR12 0xA444802C 925 #define RSPR13 0xA444802D 926 #define RSPR14 0xA444802E 927 #define RSPR15 0xA444802F 928 #define RSPR16 0xA4448030 929 #define RSPRD 0xA4448031 930 #define DTOUTR 0xA4448032 931 #define DR 0xA4448040 932 #define FIFOCLR 0xA4448042 933 #define DMACR 0xA4448044 934 #define INTCR2 0xA4448046 935 #define INTSTR2 0xA4448048 936 937 /* Z3D3 */ 938 #define DLBI 0xFD980000 939 #define DLBD0 0xFD980080 940 #define DLBD1 0xFD980100 941 #define GEWM 0xFD984000 942 #define ICD0 0xFD988000 943 #define ICD1 0xFD989000 944 #define ICT 0xFD98A000 945 #define ILM 0xFD98C000 946 #define FLM0 0xFD98C800 947 #define FLM1 0xFD98D000 948 #define FLUT 0xFD98D800 949 #define Z3D_PC 0xFD98E400 950 #define Z3D_PCSP 0xFD98E404 951 #define Z3D_PAR 0xFD98E408 952 #define Z3D_IMADR 0xFD98E40C 953 #define Z3D_BTR0 0xFD98E410 954 #define Z3D_BTR1 0xFD98E414 955 #define Z3D_BTR2 0xFD98E418 956 #define Z3D_BTR3 0xFD98E41C 957 #define Z3D_LC0 0xFD98E420 958 #define Z3D_LC1 0xFD98E424 959 #define Z3D_LC2 0xFD98E428 960 #define Z3D_LC3 0xFD98E42C 961 #define Z3D_FR0 0xFD98E430 962 #define Z3D_FR1 0xFD98E434 963 #define Z3D_FR2 0xFD98E438 964 #define Z3D_SR 0xFD98E440 965 #define Z3D_SMDR 0xFD98E444 966 #define Z3D_PBIR 0xFD98E448 967 #define Z3D_DMDR 0xFD98E44C 968 #define Z3D_IREG 0xFD98E460 969 #define Z3D_AR00 0xFD98E480 970 #define Z3D_AR01 0xFD98E484 971 #define Z3D_AR02 0xFD98E488 972 #define Z3D_AR03 0xFD98E48C 973 #define Z3D_BR00 0xFD98E490 974 #define Z3D_BR01 0xFD98E494 975 #define Z3D_IXR00 0xFD98E4A0 976 #define Z3D_IXR01 0xFD98E4A4 977 #define Z3D_IXR02 0xFD98E4A8 978 #define Z3D_IXR03 0xFD98E4AC 979 #define Z3D_AR10 0xFD98E4C0 980 #define Z3D_AR11 0xFD98E4C4 981 #define Z3D_AR12 0xFD98E4C8 982 #define Z3D_AR13 0xFD98E4CC 983 #define Z3D_BR10 0xFD98E4D0 984 #define Z3D_BR11 0xFD98E4D4 985 #define Z3D_IXR10 0xFD98E4E0 986 #define Z3D_IXR11 0xFD98E4E4 987 #define Z3D_IXR12 0xFD98E4E8 988 #define Z3D_IXR13 0xFD98E4EC 989 #define Z3D_AR20 0xFD98E500 990 #define Z3D_AR21 0xFD98E504 991 #define Z3D_AR22 0xFD98E508 992 #define Z3D_AR23 0xFD98E50C 993 #define Z3D_BR20 0xFD98E510 994 #define Z3D_BR21 0xFD98E514 995 #define Z3D_IXR20 0xFD98E520 996 #define Z3D_IXR21 0xFD98E524 997 #define Z3D_IXR22 0xFD98E528 998 #define Z3D_IXR23 0xFD98E52C 999 #define Z3D_MR0 0xFD98E540 1000 #define Z3D_MR1 0xFD98E544 1001 #define Z3D_MR2 0xFD98E548 1002 #define Z3D_MR3 0xFD98E54C 1003 #define Z3D_WORKRST 0xFD98E558 1004 #define Z3D_WORKWST 0xFD98E55C 1005 #define Z3D_DBADR 0xFD98E560 1006 #define Z3D_DLBPRST 0xFD98E564 1007 #define Z3D_DLBRST 0xFD98E568 1008 #define Z3D_DLBWST 0xFD98E56C 1009 #define Z3D_UDR0 0xFD98E570 1010 #define Z3D_UDR1 0xFD98E574 1011 #define Z3D_UDR2 0xFD98E578 1012 #define Z3D_UDR3 0xFD98E57C 1013 #define Z3D_CCR0 0xFD98E580 1014 #define Z3D_CCR1 0xFD98E584 1015 #define Z3D_EXPR 0xFD98E588 1016 #define Z3D_V0_X 0xFD9A0000 1017 #define Z3D_V0_Y 0xFD9A0004 1018 #define Z3D_V0_Z 0xFD9A0008 1019 #define Z3D_V0_W 0xFD9A000C 1020 #define Z3D_V0_A 0xFD9A0010 1021 #define Z3D_V0_R 0xFD9A0014 1022 #define Z3D_V0_G 0xFD9A0018 1023 #define Z3D_V0_B 0xFD9A001C 1024 #define Z3D_V0_F 0xFD9A0020 1025 #define Z3D_V0_SR 0xFD9A0024 1026 #define Z3D_V0_SG 0xFD9A0028 1027 #define Z3D_V0_SB 0xFD9A002C 1028 #define Z3D_V0_U0 0xFD9A0030 1029 #define Z3D_V0_V0 0xFD9A0034 1030 #define Z3D_V0_U1 0xFD9A0038 1031 #define Z3D_V0_V1 0xFD9A003C 1032 #define Z3D_V1_X 0xFD9A0080 1033 #define Z3D_V1_Y 0xFD9A0084 1034 #define Z3D_V1_Z 0xFD9A0088 1035 #define Z3D_V1_W 0xFD9A008C 1036 #define Z3D_V1_A 0xFD9A0090 1037 #define Z3D_V1_R 0xFD9A0094 1038 #define Z3D_V1_G 0xFD9A0098 1039 #define Z3D_V1_B 0xFD9A009C 1040 #define Z3D_V1_F 0xFD9A00A0 1041 #define Z3D_V1_SR 0xFD9A00A4 1042 #define Z3D_V1_SG 0xFD9A00A8 1043 #define Z3D_V1_SB 0xFD9A00AC 1044 #define Z3D_V1_U0 0xFD9A00B0 1045 #define Z3D_V1_V0 0xFD9A00B4 1046 #define Z3D_V1_U1 0xFD9A00B8 1047 #define Z3D_V1_V1 0xFD9A00BC 1048 #define Z3D_V2_X 0xFD9A0100 1049 #define Z3D_V2_Y 0xFD9A0104 1050 #define Z3D_V2_Z 0xFD9A0108 1051 #define Z3D_V2_W 0xFD9A010C 1052 #define Z3D_V2_A 0xFD9A0110 1053 #define Z3D_V2_R 0xFD9A0114 1054 #define Z3D_V2_G 0xFD9A0118 1055 #define Z3D_V2_B 0xFD9A011C 1056 #define Z3D_V2_F 0xFD9A0120 1057 #define Z3D_V2_SR 0xFD9A0124 1058 #define Z3D_V2_SG 0xFD9A0128 1059 #define Z3D_V2_SB 0xFD9A012C 1060 #define Z3D_V2_U0 0xFD9A0130 1061 #define Z3D_V2_V0 0xFD9A0134 1062 #define Z3D_V2_U1 0xFD9A0138 1063 #define Z3D_V2_V1 0xFD9A013C 1064 #define Z3D_RENDER 0xFD9A0180 1065 #define Z3D_POLYGON_OFFSET 0xFD9A0184 1066 #define Z3D_VERTEX_CONTROL 0xFD9A0200 1067 #define Z3D_STATE_MODE 0xFD9A0204 1068 #define Z3D_FPU_MODE 0xFD9A0318 1069 #define Z3D_SCISSOR_MIN 0xFD9A0400 1070 #define Z3D_SCISSOR_MAX 0xFD9A0404 1071 #define Z3D_TEXTURE_MODE_A 0xFD9A0408 1072 #define Z3D_TEXTURE_MODE_B 0xFD9A040C 1073 #define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 1074 #define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C 1075 #define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 1076 #define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 1077 #define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 1078 #define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C 1079 #define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 1080 #define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 1081 #define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 1082 #define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C 1083 #define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 1084 #define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 1085 #define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 1086 #define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C 1087 #define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 1088 #define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 1089 #define Z3D_TEXTURE_FLUSH 0xFD9A0498 1090 #define Z3D_GAMMA_TABLE0 0xFD9A049C 1091 #define Z3D_GAMMA_TABLE1 0xFD9A04A0 1092 #define Z3D_GAMMA_TABLE2 0xFD9A04A4 1093 #define Z3D_ALPHA_TEST 0xFD9A0800 1094 #define Z3D_STENCIL_TEST 0xFD9A0804 1095 #define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 1096 #define Z3D_MASK 0xFD9A080C 1097 #define Z3D_FBUS_MODE 0xFD9A0810 1098 #define Z3D_GNT_SET 0xFD9A0814 1099 #define Z3D_BETWEEN_TEST 0xFD9A0818 1100 #define Z3D_FB_BASE 0xFD9A081C 1101 #define Z3D_LCD_SIZE 0xFD9A0820 1102 #define Z3D_FB_FLUSH 0xFD9A0824 1103 #define Z3D_CACHE_INVALID 0xFD9A0828 1104 #define Z3D_SC_MODE 0xFD9A0830 1105 #define Z3D_SC0_MIN 0xFD9A0834 1106 #define Z3D_SC0_MAX 0xFD9A0838 1107 #define Z3D_SC1_MIN 0xFD9A083C 1108 #define Z3D_SC1_MAX 0xFD9A0840 1109 #define Z3D_SC2_MIN 0xFD9A0844 1110 #define Z3D_SC2_MAX 0xFD9A0848 1111 #define Z3D_SC3_MIN 0xFD9A084C 1112 #define Z3D_SC3_MAX 0xFD9A0850 1113 #define Z3D_READRESET 0xFD9A0854 1114 #define Z3D_DET_MIN 0xFD9A0858 1115 #define Z3D_DET_MAX 0xFD9A085C 1116 #define Z3D_FB_BASE_SR 0xFD9A0860 1117 #define Z3D_LCD_SIZE_SR 0xFD9A0864 1118 #define Z3D_2D_CTRL_STATUS 0xFD9A0C00 1119 #define Z3D_2D_SIZE 0xFD9A0C04 1120 #define Z3D_2D_SRCLOC 0xFD9A0C08 1121 #define Z3D_2D_DSTLOC 0xFD9A0C0C 1122 #define Z3D_2D_DMAPORT 0xFD9A0C10 1123 #define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 1124 #define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 1125 #define Z3D_2D_STPCOLOR0 0xFD9A0C1C 1126 #define Z3D_2D_STPCOLOR1 0xFD9A0C20 1127 #define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 1128 #define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 1129 #define Z3D_2D_STPPAT_0 0xFD9A0C40 1130 #define Z3D_2D_STPPAT_1 0xFD9A0C44 1131 #define Z3D_2D_STPPAT_2 0xFD9A0C48 1132 #define Z3D_2D_STPPAT_3 0xFD9A0C4C 1133 #define Z3D_2D_STPPAT_4 0xFD9A0C50 1134 #define Z3D_2D_STPPAT_5 0xFD9A0C54 1135 #define Z3D_2D_STPPAT_6 0xFD9A0C58 1136 #define Z3D_2D_STPPAT_7 0xFD9A0C5C 1137 #define Z3D_2D_STPPAT_8 0xFD9A0C60 1138 #define Z3D_2D_STPPAT_9 0xFD9A0C64 1139 #define Z3D_2D_STPPAT_10 0xFD9A0C68 1140 #define Z3D_2D_STPPAT_11 0xFD9A0C6C 1141 #define Z3D_2D_STPPAT_12 0xFD9A0C70 1142 #define Z3D_2D_STPPAT_13 0xFD9A0C74 1143 #define Z3D_2D_STPPAT_14 0xFD9A0C78 1144 #define Z3D_2D_STPPAT_15 0xFD9A0C7C 1145 #define Z3D_2D_STPPAT_16 0xFD9A0C80 1146 #define Z3D_2D_STPPAT_17 0xFD9A0C84 1147 #define Z3D_2D_STPPAT_18 0xFD9A0C88 1148 #define Z3D_2D_STPPAT_19 0xFD9A0C8C 1149 #define Z3D_2D_STPPAT_20 0xFD9A0C90 1150 #define Z3D_2D_STPPAT_21 0xFD9A0C94 1151 #define Z3D_2D_STPPAT_22 0xFD9A0C98 1152 #define Z3D_2D_STPPAT_23 0xFD9A0C9C 1153 #define Z3D_2D_STPPAT_24 0xFD9A0CA0 1154 #define Z3D_2D_STPPAT_25 0xFD9A0CA4 1155 #define Z3D_2D_STPPAT_26 0xFD9A0CA8 1156 #define Z3D_2D_STPPAT_27 0xFD9A0CAC 1157 #define Z3D_2D_STPPAT_28 0xFD9A0CB0 1158 #define Z3D_2D_STPPAT_29 0xFD9A0CB4 1159 #define Z3D_2D_STPPAT_30 0xFD9A0CB8 1160 #define Z3D_2D_STPPAT_31 0xFD9A0CBC 1161 #define Z3D_WR_CTRL 0xFD9A1000 1162 #define Z3D_WR_P0 0xFD9A1004 1163 #define Z3D_WR_P1 0xFD9A1008 1164 #define Z3D_WR_P2 0xFD9A100C 1165 #define Z3D_WR_FGC 0xFD9A1010 1166 #define Z3D_WR_BGC 0xFD9A1014 1167 #define Z3D_WR_SZ 0xFD9A1018 1168 #define Z3D_WR_PATPARAM 0xFD9A101C 1169 #define Z3D_WR_PAT 0xFD9A1020 1170 #define Z3D_SYS_STATUS 0xFD9A1400 1171 #define Z3D_SYS_RESET 0xFD9A1404 1172 #define Z3D_SYS_CLK 0xFD9A1408 1173 #define Z3D_SYS_CONF 0xFD9A140C 1174 #define Z3D_SYS_VERSION 0xFD9A1410 1175 #define Z3D_SYS_DBINV 0xFD9A1418 1176 #define Z3D_SYS_I2F_FMT 0xFD9A1420 1177 #define Z3D_SYS_I2F_SRC 0xFD9A1424 1178 #define Z3D_SYS_I2F_DST 0xFD9A1428 1179 #define Z3D_SYS_GBCNT 0xFD9A1430 1180 #define Z3D_SYS_BSYCNT 0xFD9A1434 1181 #define Z3D_SYS_INT_STATUS 0xFD9A1450 1182 #define Z3D_SYS_INT_MASK 0xFD9A1454 1183 #define Z3D_SYS_INT_CLEAR 0xFD9A1458 1184 #define TCD0 0xFD9C0000 1185 #define TCD1 0xFD9C0400 1186 #define TCD2 0xFD9C0800 1187 #define TCD3 0xFD9C0C00 1188 #define TCT0 0xFD9C1000 1189 #define TCT1 0xFD9C1400 1190 #define TCT2 0xFD9C1800 1191 #define TCT3 0xFD9C1C00 1192 1193 /* PFC */ 1194 #define PACR 0xA4050100 1195 #define PBCR 0xA4050102 1196 #define PCCR 0xA4050104 1197 #define PDCR 0xA4050106 1198 #define PECR 0xA4050108 1199 #define PFCR 0xA405010A 1200 #define PGCR 0xA405010C 1201 #define PHCR 0xA405010E 1202 #define PJCR 0xA4050110 1203 #define PKCR 0xA4050112 1204 #define PLCR 0xA4050114 1205 #define PMCR 0xA4050116 1206 #define PNCR 0xA4050118 1207 #define PQCR 0xA405011A 1208 #define PRCR 0xA405011C 1209 #define PSCR 0xA405011E 1210 #define PTCR 0xA4050140 1211 #define PUCR 0xA4050142 1212 #define PVCR 0xA4050144 1213 #define PWCR 0xA4050146 1214 #define PXCR 0xA4050148 1215 #define PYCR 0xA405014A 1216 #define PZCR 0xA405014C 1217 #define PSELA 0xA405014E 1218 #define PSELB 0xA4050150 1219 #define PSELC 0xA4050152 1220 #define PSELD 0xA4050154 1221 #define PSELE 0xA4050156 1222 #define HIZCRA 0xA4050158 1223 #define HIZCRB 0xA405015A 1224 #define HIZCRC 0xA405015C 1225 #define HIZCRC 0xA405015C 1226 #define MSELCRA 0xA4050180 1227 #define MSELCRB 0xA4050182 1228 #define PULCR 0xA4050184 1229 #define SBSCR 0xA4050186 1230 #define DRVCR 0xA405018A 1231 1232 /* I/O Port */ 1233 #define PADR 0xA4050120 1234 #define PBDR 0xA4050122 1235 #define PCDR 0xA4050124 1236 #define PDDR 0xA4050126 1237 #define PEDR 0xA4050128 1238 #define PFDR 0xA405012A 1239 #define PGDR 0xA405012C 1240 #define PHDR 0xA405012E 1241 #define PJDR 0xA4050130 1242 #define PKDR 0xA4050132 1243 #define PLDR 0xA4050134 1244 #define PMDR 0xA4050136 1245 #define PNDR 0xA4050138 1246 #define PQDR 0xA405013A 1247 #define PRDR 0xA405013C 1248 #define PSDR 0xA405013E 1249 #define PTDR 0xA4050160 1250 #define PUDR 0xA4050162 1251 #define PVDR 0xA4050164 1252 #define PWDR 0xA4050166 1253 #define PXDR 0xA4050168 1254 #define PYDR 0xA405016A 1255 #define PZDR 0xA405016C 1256 1257 /* UBC */ 1258 #define CBR0 0xFF200000 1259 #define CRR0 0xFF200004 1260 #define CAR0 0xFF200008 1261 #define CAMR0 0xFF20000C 1262 #define CBR1 0xFF200020 1263 #define CRR1 0xFF200024 1264 #define CAR1 0xFF200028 1265 #define CAMR1 0xFF20002C 1266 #define CDR1 0xFF200030 1267 #define CDMR1 0xFF200034 1268 #define CETR1 0xFF200038 1269 #define CCMFR 0xFF200600 1270 #define CBCR 0xFF200620 1271 1272 /* H-UDI */ 1273 #define SDIR 0xFC110000 1274 #define SDDRH 0xFC110008 1275 #define SDDRL 0xFC11000A 1276 #define SDINT 0xFC110018 1277 1278 #endif /* _ASM_CPU_SH7722_H_ */ 1279