1 /* 2 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 3 * 4 * SH7722 Internal I/O register 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef _ASM_CPU_SH7722_H_ 23 #define _ASM_CPU_SH7722_H_ 24 25 #define CACHE_OC_NUM_WAYS 4 26 #define CCR_CACHE_INIT 0x0000090d 27 28 /* EXP */ 29 #define TRA 0xFF000020 30 #define EXPEVT 0xFF000024 31 #define INTEVT 0xFF000028 32 33 /* MMU */ 34 #define PTEH 0xFF000000 35 #define PTEL 0xFF000004 36 #define TTB 0xFF000008 37 #define TEA 0xFF00000C 38 #define MMUCR 0xFF000010 39 #define PASCR 0xFF000070 40 #define IRMCR 0xFF000078 41 42 /* CACHE */ 43 #define CCR 0xFF00001C 44 #define RAMCR 0xFF000074 45 46 /* XY MEMORY */ 47 #define XSA 0xFF000050 48 #define YSA 0xFF000054 49 #define XDA 0xFF000058 50 #define YDA 0xFF00005C 51 #define XPR 0xFF000060 52 #define YPR 0xFF000064 53 #define XEA 0xFF000068 54 #define YEA 0xFF00006C 55 56 /* INTC */ 57 #define ICR0 0xA4140000 58 #define ICR1 0xA414001C 59 #define INTPRI0 0xA4140010 60 #define INTREQ0 0xA4140024 61 #define INTMSK0 0xA4140044 62 #define INTMSKCLR0 0xA4140064 63 #define NMIFCR 0xA41400C0 64 #define USERIMASK 0xA4700000 65 #define IPRA 0xA4080000 66 #define IPRB 0xA4080004 67 #define IPRC 0xA4080008 68 #define IPRD 0xA408000C 69 #define IPRE 0xA4080010 70 #define IPRF 0xA4080014 71 #define IPRG 0xA4080018 72 #define IPRH 0xA408001C 73 #define IPRI 0xA4080020 74 #define IPRJ 0xA4080024 75 #define IPRK 0xA4080028 76 #define IPRL 0xA408002C 77 #define IMR0 0xA4080080 78 #define IMR1 0xA4080084 79 #define IMR2 0xA4080088 80 #define IMR3 0xA408008C 81 #define IMR4 0xA4080090 82 #define IMR5 0xA4080094 83 #define IMR6 0xA4080098 84 #define IMR7 0xA408009C 85 #define IMR8 0xA40800A0 86 #define IMR9 0xA40800A4 87 #define IMR10 0xA40800A8 88 #define IMR11 0xA40800AC 89 #define IMCR0 0xA40800C0 90 #define IMCR1 0xA40800C4 91 #define IMCR2 0xA40800C8 92 #define IMCR3 0xA40800CC 93 #define IMCR4 0xA40800D0 94 #define IMCR5 0xA40800D4 95 #define IMCR6 0xA40800D8 96 #define IMCR7 0xA40800DC 97 #define IMCR8 0xA40800E0 98 #define IMCR9 0xA40800E4 99 #define IMCR10 0xA40800E8 100 #define IMCR11 0xA40800EC 101 #define MFI_IPRA 0xA40B0000 102 #define MFI_IPRB 0xA40B0004 103 #define MFI_IPRC 0xA40B0008 104 #define MFI_IPRD 0xA40B000C 105 #define MFI_IPRE 0xA40B0010 106 #define MFI_IPRF 0xA40B0014 107 #define MFI_IPRG 0xA40B0018 108 #define MFI_IPRH 0xA40B001C 109 #define MFI_IPRI 0xA40B0020 110 #define MFI_IPRJ 0xA40B0024 111 #define MFI_IPRK 0xA40B0028 112 #define MFI_IPRL 0xA40B002C 113 #define MFI_IMR0 0xA40B0080 114 #define MFI_IMR1 0xA40B0084 115 #define MFI_IMR2 0xA40B0088 116 #define MFI_IMR3 0xA40B008C 117 #define MFI_IMR4 0xA40B0090 118 #define MFI_IMR5 0xA40B0094 119 #define MFI_IMR6 0xA40B0098 120 #define MFI_IMR7 0xA40B009C 121 #define MFI_IMR8 0xA40B00A0 122 #define MFI_IMR9 0xA40B00A4 123 #define MFI_IMR10 0xA40B00A8 124 #define MFI_IMR11 0xA40B00AC 125 #define MFI_IMCR0 0xA40B00C0 126 #define MFI_IMCR1 0xA40B00C4 127 #define MFI_IMCR2 0xA40B00C8 128 #define MFI_IMCR3 0xA40B00CC 129 #define MFI_IMCR4 0xA40B00D0 130 #define MFI_IMCR5 0xA40B00D4 131 #define MFI_IMCR6 0xA40B00D8 132 #define MFI_IMCR7 0xA40B00DC 133 #define MFI_IMCR8 0xA40B00E0 134 #define MFI_IMCR9 0xA40B00E4 135 #define MFI_IMCR10 0xA40B00E8 136 #define MFI_IMCR11 0xA40B00EC 137 138 /* BSC */ 139 #define CMNCR 0xFEC10000 140 #define CS0BCR 0xFEC10004 141 #define CS2BCR 0xFEC10008 142 #define CS4BCR 0xFEC10010 143 #define CS5ABCR 0xFEC10014 144 #define CS5BBCR 0xFEC10018 145 #define CS6ABCR 0xFEC1001C 146 #define CS6BBCR 0xFEC10020 147 #define CS0WCR 0xFEC10024 148 #define CS2WCR 0xFEC10028 149 #define CS4WCR 0xFEC10030 150 #define CS5AWCR 0xFEC10034 151 #define CS5BWCR 0xFEC10038 152 #define CS6AWCR 0xFEC1003C 153 #define CS6BWCR 0xFEC10040 154 #define RBWTCNT 0xFEC10054 155 156 /* SBSC */ 157 #define SBSC_SDCR 0xFE400008 158 #define SBSC_SDWCR 0xFE40000C 159 #define SBSC_SDPCR 0xFE400010 160 #define SBSC_RTCSR 0xFE400014 161 #define SBSC_RTCNT 0xFE400018 162 #define SBSC_RTCOR 0xFE40001C 163 #define SBSC_RFCR 0xFE400020 164 165 /* DMAC */ 166 #define SAR_0 0xFE008020 167 #define DAR_0 0xFE008024 168 #define TCR_0 0xFE008028 169 #define CHCR_0 0xFE00802C 170 #define SAR_1 0xFE008030 171 #define DAR_1 0xFE008034 172 #define TCR_1 0xFE008038 173 #define CHCR_1 0xFE00803C 174 #define SAR_2 0xFE008040 175 #define DAR_2 0xFE008044 176 #define TCR_2 0xFE008048 177 #define CHCR_2 0xFE00804C 178 #define SAR_3 0xFE008050 179 #define DAR_3 0xFE008054 180 #define TCR_3 0xFE008058 181 #define CHCR_3 0xFE00805C 182 #define SAR_4 0xFE008070 183 #define DAR_4 0xFE008074 184 #define TCR_4 0xFE008078 185 #define CHCR_4 0xFE00807C 186 #define SAR_5 0xFE008080 187 #define DAR_5 0xFE008084 188 #define TCR_5 0xFE008088 189 #define CHCR_5 0xFE00808C 190 #define SARB_0 0xFE008120 191 #define DARB_0 0xFE008124 192 #define TCRB_0 0xFE008128 193 #define SARB_1 0xFE008130 194 #define DARB_1 0xFE008134 195 #define TCRB_1 0xFE008138 196 #define SARB_2 0xFE008140 197 #define DARB_2 0xFE008144 198 #define TCRB_2 0xFE008148 199 #define SARB_3 0xFE008150 200 #define DARB_3 0xFE008154 201 #define TCRB_3 0xFE008158 202 #define DMAOR 0xFE008060 203 #define DMARS_0 0xFE009000 204 #define DMARS_1 0xFE009004 205 #define DMARS_2 0xFE009008 206 207 /* CPG */ 208 #define FRQCR 0xA4150000 209 #define VCLKCR 0xA4150004 210 #define SCLKACR 0xA4150008 211 #define SCLKBCR 0xA415000C 212 #define PLLCR 0xA4150024 213 #define DLLFRQ 0xA4150050 214 215 /* LOW POWER MODE */ 216 #define STBCR 0xA4150020 217 #define MSTPCR0 0xA4150030 218 #define MSTPCR1 0xA4150034 219 #define MSTPCR2 0xA4150038 220 #define BAR 0xA4150040 221 222 /* RWDT */ 223 #define RWTCNT 0xA4520000 224 #define RWTCSR 0xA4520004 225 #define WTCNT RWTCNT 226 227 228 /* TMU */ 229 #define TMU_BASE 0xFFD80000 230 231 /* TPU */ 232 #define TPU_TSTR 0xA4C90000 233 #define TPU_TCR0 0xA4C90010 234 #define TPU_TMDR0 0xA4C90014 235 #define TPU_TIOR0 0xA4C90018 236 #define TPU_TIER0 0xA4C9001C 237 #define TPU_TSR0 0xA4C90020 238 #define TPU_TCNT0 0xA4C90024 239 #define TPU_TGR0A 0xA4C90028 240 #define TPU_TGR0B 0xA4C9002C 241 #define TPU_TGR0C 0xA4C90030 242 #define TPU_TGR0D 0xA4C90034 243 #define TPU_TCR1 0xA4C90050 244 #define TPU_TMDR1 0xA4C90054 245 #define TPU_TIER1 0xA4C9005C 246 #define TPU_TSR1 0xA4C90060 247 #define TPU_TCNT1 0xA4C90064 248 #define TPU_TGR1A 0xA4C90068 249 #define TPU_TGR1B 0xA4C9006C 250 #define TPU_TGR1C 0xA4C90070 251 #define TPU_TGR1D 0xA4C90074 252 #define TPU_TCR2 0xA4C90090 253 #define TPU_TMDR2 0xA4C90094 254 #define TPU_TIER2 0xA4C9009C 255 #define TPU_TSR2 0xA4C900A0 256 #define TPU_TCNT2 0xA4C900A4 257 #define TPU_TGR2A 0xA4C900A8 258 #define TPU_TGR2B 0xA4C900AC 259 #define TPU_TGR2C 0xA4C900B0 260 #define TPU_TGR2D 0xA4C900B4 261 #define TPU_TCR3 0xA4C900D0 262 #define TPU_TMDR3 0xA4C900D4 263 #define TPU_TIER3 0xA4C900DC 264 #define TPU_TSR3 0xA4C900E0 265 #define TPU_TCNT3 0xA4C900E4 266 #define TPU_TGR3A 0xA4C900E8 267 #define TPU_TGR3B 0xA4C900EC 268 #define TPU_TGR3C 0xA4C900F0 269 #define TPU_TGR3D 0xA4C900F4 270 271 /* CMT */ 272 #define CMSTR 0xA44A0000 273 #define CMCSR 0xA44A0060 274 #define CMCNT 0xA44A0064 275 #define CMCOR 0xA44A0068 276 277 /* SIO */ 278 #define SIOMDR 0xA4500000 279 #define SIOCTR 0xA4500004 280 #define SIOSTBCR0 0xA4500008 281 #define SIOSTBCR1 0xA450000C 282 #define SIOTDR 0xA4500014 283 #define SIORDR 0xA4500018 284 #define SIOSTR 0xA450001C 285 #define SIOIER 0xA4500020 286 #define SIOSCR 0xA4500024 287 288 /* SIOF */ 289 #define SIMDR0 0xA4410000 290 #define SISCR0 0xA4410002 291 #define SITDAR0 0xA4410004 292 #define SIRDAR0 0xA4410006 293 #define SICDAR0 0xA4410008 294 #define SICTR0 0xA441000C 295 #define SIFCTR0 0xA4410010 296 #define SISTR0 0xA4410014 297 #define SIIER0 0xA4410016 298 #define SITDR0 0xA4410020 299 #define SIRDR0 0xA4410024 300 #define SITCR0 0xA4410028 301 #define SIRCR0 0xA441002C 302 #define SPICR0 0xA4410030 303 #define SIMDR1 0xA4420000 304 #define SISCR1 0xA4420002 305 #define SITDAR1 0xA4420004 306 #define SIRDAR1 0xA4420006 307 #define SICDAR1 0xA4420008 308 #define SICTR1 0xA442000C 309 #define SIFCTR1 0xA4420010 310 #define SISTR1 0xA4420014 311 #define SIIER1 0xA4420016 312 #define SITDR1 0xA4420020 313 #define SIRDR1 0xA4420024 314 #define SITCR1 0xA4420028 315 #define SIRCR1 0xA442002C 316 #define SPICR1 0xA4420030 317 318 /* SCIF */ 319 #define SCIF0_BASE 0xFFE00000 320 321 /* SIM */ 322 #define SIM_SCSMR 0xA4490000 323 #define SIM_SCBRR 0xA4490002 324 #define SIM_SCSCR 0xA4490004 325 #define SIM_SCTDR 0xA4490006 326 #define SIM_SCSSR 0xA4490008 327 #define SIM_SCRDR 0xA449000A 328 #define SIM_SCSCMR 0xA449000C 329 #define SIM_SCSC2R 0xA449000E 330 #define SIM_SCWAIT 0xA4490010 331 #define SIM_SCGRD 0xA4490012 332 #define SIM_SCSMPL 0xA4490014 333 #define SIM_SCDMAEN 0xA4490016 334 335 /* IrDA */ 336 #define IRIF_INIT1 0xA45D0012 337 #define IRIF_INIT2 0xA45D0014 338 #define IRIF_RINTCLR 0xA45D0016 339 #define IRIF_TINTCLR 0xA45D0018 340 #define IRIF_SIR0 0xA45D0020 341 #define IRIF_SIR1 0xA45D0022 342 #define IRIF_SIR2 0xA45D0024 343 #define IRIF_SIR3 0xA45D0026 344 #define IRIF_SIR_FRM 0xA45D0028 345 #define IRIF_SIR_EOF 0xA45D002A 346 #define IRIF_SIR_FLG 0xA45D002C 347 #define IRIF_SIR_STS2 0xA45D002E 348 #define IRIF_UART0 0xA45D0030 349 #define IRIF_UART1 0xA45D0032 350 #define IRIF_UART2 0xA45D0034 351 #define IRIF_UART3 0xA45D0036 352 #define IRIF_UART4 0xA45D0038 353 #define IRIF_UART5 0xA45D003A 354 #define IRIF_UART6 0xA45D003C 355 #define IRIF_UART7 0xA45D003E 356 #define IRIF_CRC0 0xA45D0040 357 #define IRIF_CRC1 0xA45D0042 358 #define IRIF_CRC2 0xA45D0044 359 #define IRIF_CRC3 0xA45D0046 360 #define IRIF_CRC4 0xA45D0048 361 362 /* IIC */ 363 #define ICDR0 0xA4470000 364 #define ICCR0 0xA4470004 365 #define ICSR0 0xA4470008 366 #define ICIC0 0xA447000C 367 #define ICCL0 0xA4470010 368 #define ICCH0 0xA4470014 369 #define ICDR1 0xA4750000 370 #define ICCR1 0xA4750004 371 #define ICSR1 0xA4750008 372 #define ICIC1 0xA475000C 373 #define ICCL1 0xA4750010 374 #define ICCH1 0xA4750014 375 376 /* FLCTL */ 377 #define FLCMNCR 0xA4530000 378 #define FLCMDCR 0xA4530004 379 #define FLCMCDR 0xA4530008 380 #define FLADR 0xA453000C 381 #define FLDATAR 0xA4530010 382 #define FLDTCNTR 0xA4530014 383 #define FLINTDMACR 0xA4530018 384 #define FLBSYTMR 0xA453001C 385 #define FLBSYCNT 0xA4530020 386 #define FLDTFIFO 0xA4530024 387 #define FLECFIFO 0xA4530028 388 #define FLTRCR 0xA453002C 389 #define FLADR2 0xA453003C 390 391 /* MFI */ 392 #define MFIIDX 0xA4C10000 393 #define MFIGSR 0xA4C10004 394 #define MFISCR 0xA4C10008 395 #define MFIMCR 0xA4C1000C 396 #define MFIIICR 0xA4C10010 397 #define MFIEICR 0xA4C10014 398 #define MFIADR 0xA4C10018 399 #define MFIDATA 0xA4C1001C 400 #define MFIRCR 0xA4C10020 401 #define MFIINTEVT 0xA4C1002C 402 #define MFIIMASK 0xA4C10030 403 #define MFIBCR 0xA4C10040 404 #define MFIADRW 0xA4C10044 405 #define MFIADRR 0xA4C10048 406 #define MFIDATAW 0xA4C1004C 407 #define MFIDATAR 0xA4C10050 408 #define MFIMCRW 0xA4C10054 409 #define MFIMCRR 0xA4C10058 410 #define MFIDNRW 0xA4C1005C 411 #define MFIDNRR 0xA4C10060 412 #define MFISIZEW 0xA4C10064 413 #define MFISIZER 0xA4C10068 414 #define MFIDEVCR 0xA4C10038 415 #define MFISM4 0xA4C10080 416 417 /* VPU */ 418 #define VP4_CTRL 0xFE900000 419 #define VP4_VOL_CTRL 0xFE900004 420 #define VP4_IMAGE_SIZE 0xFE900008 421 #define VP4_MB_NUM 0xFE90000C 422 #define VP4_DWY_ADDR 0xFE900010 423 #define VP4_DWC_ADDR 0xFE900014 424 #define VP4_D2WY_ADDR 0xFE900018 425 #define VP4_D2WC_ADDR 0xFE90001C 426 #define VP4_DP1_ADDR 0xFE900020 427 #define VP4_DP2_ADDR 0xFE900024 428 #define VP4_STRS_ADDR 0xFE900028 429 #define VP4_STRE_ADDR 0xFE90002C 430 #define VP4_VOP_CTRL 0xFE900030 431 #define VP4_VOP_TIME 0xFE900034 432 #define VP4_263_CTRL 0xFE900038 433 #define VP4_264_CTRL 0xFE90003C 434 #define VP4_VLC_CTRL 0xFE900040 435 #define VP4_ENDIAN 0xFE900044 436 #define VP4_CMD 0xFE900048 437 #define VP4_ME_TH1 0xFE90004C 438 #define VP4_ME_TH2 0xFE900050 439 #define VP4_ME_COSTMB 0xFE900054 440 #define VP4_ME_SKIP 0xFE900058 441 #define VP4_ME_CTRL 0xFE90005C 442 #define VP4_MBRF_CTRL 0xFE900060 443 #define VP4_MC_CTRL 0xFE900064 444 #define VP4_PRED_CTRL 0xFE900068 445 #define VP4_SLC_SIZE 0xFE90006C 446 #define VP4_VOP_MINBIT 0xFE900070 447 #define VP4_MB_MAXBIT 0xFE900074 448 #define VP4_MB_TBIT 0xFE900078 449 #define VP4_RCQNT 0xFE90007C 450 #define VP4_RCRP 0xFE900080 451 #define VP4_RCDJ 0xFE900084 452 #define VP4_RCWQ 0xFE900088 453 #define VP4_FWD_TIME 0xFE900094 454 #define VP4_BWD_TIME 0xFE900098 455 #define VP4_PST_TIME 0xFE90009C 456 #define VP4_ILTFRAME 0xFE9000A0 457 #define VP4_EC_REF 0xFE9000A4 458 #define VP4_STATUS 0xFE900100 459 #define VP4_IRQ_ENB 0xFE900104 460 #define VP4_IRQ_STA 0xFE900108 461 #define VP4_VOP_BIT 0xFE90010C 462 #define VP4_PRV_BIT 0xFE900110 463 #define VP4_SLC_MB 0xFE900114 464 #define VP4_QSUM 0xFE900118 465 #define VP4_DEC_ERR 0xFE90011C 466 #define VP4_ERR_AREA 0xFE900120 467 #define VP4_NEXT_CODE 0xFE900124 468 #define VP4_MB_ATTR 0xFE900128 469 #define VP4_DBMON 0xFE90012C 470 #define VP4_DEBUG 0xFE900130 471 #define VP4_ERR_DET 0xFE900134 472 #define VP4_CLK_STOP 0xFE900138 473 #define VP4_MB_SADA 0xFE90013C 474 #define VP4_MB_SADR 0xFE900140 475 #define VP4_MAT_RAM 0xFE901000 476 #define VP4_NC_RAM 0xFE902000 477 #define WT 0xFE9020CC 478 #define VP4_CPY_ADDR 0xFE902264 479 #define VP4_CPC_ADDR 0xFE902268 480 #define VP4_R0Y_ADDR 0xFE90226C 481 #define VP4_R0C_ADDR 0xFE902270 482 #define VP4_R1Y_ADDR 0xFE902274 483 #define VP4_R1C_ADDR 0xFE902278 484 #define VP4_R2Y_ADDR 0xFE90227C 485 #define VP4_R2C_ADDR 0xFE902280 486 #define VP4_R3Y_ADDR 0xFE902284 487 #define VP4_R3C_ADDR 0xFE902288 488 #define VP4_R4Y_ADDR 0xFE90228C 489 #define VP4_R4C_ADDR 0xFE902290 490 #define VP4_R5Y_ADDR 0xFE902294 491 #define VP4_R5C_ADDR 0xFE902298 492 #define VP4_R6Y_ADDR 0xFE90229C 493 #define VP4_R6C_ADDR 0xFE9022A0 494 #define VP4_R7Y_ADDR 0xFE9022A4 495 #define VP4_R7C_ADDR 0xFE9022A8 496 #define VP4_R8Y_ADDR 0xFE9022AC 497 #define VP4_R8C_ADDR 0xFE9022B0 498 #define VP4_R9Y_ADDR 0xFE9022B4 499 #define VP4_R9C_ADDR 0xFE9022B8 500 #define VP4_RAY_ADDR 0xFE9022BC 501 #define VP4_RAC_ADDR 0xFE9022C0 502 #define VP4_RBY_ADDR 0xFE9022C4 503 #define VP4_RBC_ADDR 0xFE9022C8 504 #define VP4_RCY_ADDR 0xFE9022CC 505 #define VP4_RCC_ADDR 0xFE9022D0 506 #define VP4_RDY_ADDR 0xFE9022D4 507 #define VP4_RDC_ADDR 0xFE9022D8 508 #define VP4_REY_ADDR 0xFE9022DC 509 #define VP4_REC_ADDR 0xFE9022E0 510 #define VP4_RFY_ADDR 0xFE9022E4 511 #define VP4_RFC_ADDR 0xFE9022E8 512 513 /* VIO(CEU) */ 514 #define CAPSR 0xFE910000 515 #define CAPCR 0xFE910004 516 #define CAMCR 0xFE910008 517 #define CMCYR 0xFE91000C 518 #define CAMOR 0xFE910010 519 #define CAPWR 0xFE910014 520 #define CAIFR 0xFE910018 521 #define CSTCR 0xFE910020 522 #define CSECR 0xFE910024 523 #define CRCNTR 0xFE910028 524 #define CRCMPR 0xFE91002C 525 #define CFLCR 0xFE910030 526 #define CFSZR 0xFE910034 527 #define CDWDR 0xFE910038 528 #define CDAYR 0xFE91003C 529 #define CDACR 0xFE910040 530 #define CDBYR 0xFE910044 531 #define CDBCR 0xFE910048 532 #define CBDSR 0xFE91004C 533 #define CLFCR 0xFE910060 534 #define CDOCR 0xFE910064 535 #define CDDCR 0xFE910068 536 #define CDDAR 0xFE91006C 537 #define CEIER 0xFE910070 538 #define CETCR 0xFE910074 539 #define CSTSR 0xFE91007C 540 #define CSRTR 0xFE910080 541 #define CDAYR2 0xFE910090 542 #define CDACR2 0xFE910094 543 #define CDBYR2 0xFE910098 544 #define CDBCR2 0xFE91009C 545 546 /* VIO(VEU) */ 547 #define VESTR 0xFE920000 548 #define VESWR 0xFE920010 549 #define VESSR 0xFE920014 550 #define VSAYR 0xFE920018 551 #define VSACR 0xFE92001C 552 #define VBSSR 0xFE920020 553 #define VEDWR 0xFE920030 554 #define VDAYR 0xFE920034 555 #define VDACR 0xFE920038 556 #define VTRCR 0xFE920050 557 #define VRFCR 0xFE920054 558 #define VRFSR 0xFE920058 559 #define VENHR 0xFE92005C 560 #define VFMCR 0xFE920070 561 #define VVTCR 0xFE920074 562 #define VHTCR 0xFE920078 563 #define VAPCR 0xFE920080 564 #define VECCR 0xFE920084 565 #define VAFXR 0xFE920090 566 #define VSWPR 0xFE920094 567 #define VEIER 0xFE9200A0 568 #define VEVTR 0xFE9200A4 569 #define VSTAR 0xFE9200B0 570 #define VBSRR 0xFE9200B4 571 572 /* VIO(BEU) */ 573 #define BESTR 0xFE930000 574 #define BSMWR1 0xFE930010 575 #define BSSZR1 0xFE930014 576 #define BSAYR1 0xFE930018 577 #define BSACR1 0xFE93001C 578 #define BSAAR1 0xFE930020 579 #define BSIFR1 0xFE930024 580 #define BSMWR2 0xFE930028 581 #define BSSZR2 0xFE93002C 582 #define BSAYR2 0xFE930030 583 #define BSACR2 0xFE930034 584 #define BSAAR2 0xFE930038 585 #define BSIFR2 0xFE93003C 586 #define BSMWR3 0xFE930040 587 #define BSSZR3 0xFE930044 588 #define BSAYR3 0xFE930048 589 #define BSACR3 0xFE93004C 590 #define BSAAR3 0xFE930050 591 #define BSIFR3 0xFE930054 592 #define BTPSR 0xFE930058 593 #define BMSMWR1 0xFE930070 594 #define BMSSZR1 0xFE930074 595 #define BMSAYR1 0xFE930078 596 #define BMSACR1 0xFE93007C 597 #define BMSMWR2 0xFE930080 598 #define BMSSZR2 0xFE930084 599 #define BMSAYR2 0xFE930088 600 #define BMSACR2 0xFE93008C 601 #define BMSMWR3 0xFE930090 602 #define BMSSZR3 0xFE930094 603 #define BMSAYR3 0xFE930098 604 #define BMSACR3 0xFE93009C 605 #define BMSMWR4 0xFE9300A0 606 #define BMSSZR4 0xFE9300A4 607 #define BMSAYR4 0xFE9300A8 608 #define BMSACR4 0xFE9300AC 609 #define BMSIFR 0xFE9300F0 610 #define BBLCR0 0xFE930100 611 #define BBLCR1 0xFE930104 612 #define BPROCR 0xFE930108 613 #define BMWCR0 0xFE93010C 614 #define BLOCR1 0xFE930114 615 #define BLOCR2 0xFE930118 616 #define BLOCR3 0xFE93011C 617 #define BMLOCR1 0xFE930120 618 #define BMLOCR2 0xFE930124 619 #define BMLOCR3 0xFE930128 620 #define BMLOCR4 0xFE93012C 621 #define BMPCCR1 0xFE930130 622 #define BMPCCR2 0xFE930134 623 #define BPKFR 0xFE930140 624 #define BPCCR0 0xFE930144 625 #define BPCCR11 0xFE930148 626 #define BPCCR12 0xFE93014C 627 #define BPCCR21 0xFE930150 628 #define BPCCR22 0xFE930154 629 #define BPCCR31 0xFE930158 630 #define BPCCR32 0xFE93015C 631 #define BDMWR 0xFE930160 632 #define BDAYR 0xFE930164 633 #define BDACR 0xFE930168 634 #define BAFXR 0xFE930180 635 #define BSWPR 0xFE930184 636 #define BEIER 0xFE930188 637 #define BEVTR 0xFE93018C 638 #define BRCNTR 0xFE930194 639 #define BSTAR 0xFE930198 640 #define BBRSTR 0xFE93019C 641 #define BRCHR 0xFE9301A0 642 #define CLUT 0xFE933000 643 644 /* JPU */ 645 #define JCMOD 0xFEA00000 646 #define JCCMD 0xFEA00004 647 #define JCSTS 0xFEA00008 648 #define JCQTN 0xFEA0000C 649 #define JCHTN 0xFEA00010 650 #define JCDRIU 0xFEA00014 651 #define JCDRID 0xFEA00018 652 #define JCVSZU 0xFEA0001C 653 #define JCVSZD 0xFEA00020 654 #define JCHSZU 0xFEA00024 655 #define JCHSZD 0xFEA00028 656 #define JCDTCU 0xFEA0002C 657 #define JCDTCM 0xFEA00030 658 #define JCDTCD 0xFEA00034 659 #define JINTE 0xFEA00038 660 #define JINTS 0xFEA0003C 661 #define JCDERR 0xFEA00040 662 #define JCRST 0xFEA00044 663 #define JIFCNT 0xFEA00060 664 #define JIFECNT 0xFEA00070 665 #define JIFESYA1 0xFEA00074 666 #define JIFESCA1 0xFEA00078 667 #define JIFESYA2 0xFEA0007C 668 #define JIFESCA2 0xFEA00080 669 #define JIFESMW 0xFEA00084 670 #define JIFESVSZ 0xFEA00088 671 #define JIFESHSZ 0xFEA0008C 672 #define JIFEDA1 0xFEA00090 673 #define JIFEDA2 0xFEA00094 674 #define JIFEDRSZ 0xFEA00098 675 #define JIFDCNT 0xFEA000A0 676 #define JIFDSA1 0xFEA000A4 677 #define JIFDSA2 0xFEA000A8 678 #define JIFDDRSZ 0xFEA000AC 679 #define JIFDDMW 0xFEA000B0 680 #define JIFDDVSZ 0xFEA000B4 681 #define JIFDDHSZ 0xFEA000B8 682 #define JIFDDYA1 0xFEA000BC 683 #define JIFDDCA1 0xFEA000C0 684 #define JIFDDYA2 0xFEA000C4 685 #define JIFDDCA2 0xFEA000C8 686 #define JCQTBL0 0xFEA10000 687 #define JCQTBL1 0xFEA10040 688 #define JCQTBL2 0xFEA10080 689 #define JCQTBL3 0xFEA100C0 690 #define JCHTBD0 0xFEA10100 691 #define JCHTBA0 0xFEA10120 692 #define JCHTBD1 0xFEA10200 693 #define JCHTBA1 0xFEA10220 694 695 /* LCDC */ 696 #define MLDDCKPAT1R 0xFE940400 697 #define MLDDCKPAT2R 0xFE940404 698 #define SLDDCKPAT1R 0xFE940408 699 #define SLDDCKPAT2R 0xFE94040C 700 #define LDDCKR 0xFE940410 701 #define LDDCKSTPR 0xFE940414 702 #define MLDMT1R 0xFE940418 703 #define MLDMT2R 0xFE94041C 704 #define MLDMT3R 0xFE940420 705 #define MLDDFR 0xFE940424 706 #define MLDSM1R 0xFE940428 707 #define MLDSM2R 0xFE94042C 708 #define MLDSA1R 0xFE940430 709 #define MLDSA2R 0xFE940434 710 #define MLDMLSR 0xFE940438 711 #define MLDWBFR 0xFE94043C 712 #define MLDWBCNTR 0xFE940440 713 #define MLDWBAR 0xFE940444 714 #define MLDHCNR 0xFE940448 715 #define MLDHSYNR 0xFE94044C 716 #define MLDVLNR 0xFE940450 717 #define MLDVSYNR 0xFE940454 718 #define MLDHPDR 0xFE940458 719 #define MLDVPDR 0xFE94045C 720 #define MLDPMR 0xFE940460 721 #define LDPALCR 0xFE940464 722 #define LDINTR 0xFE940468 723 #define LDSR 0xFE94046C 724 #define LDCNT1R 0xFE940470 725 #define LDCNT2R 0xFE940474 726 #define LDRCNTR 0xFE940478 727 #define LDDDSR 0xFE94047C 728 #define LDRCR 0xFE940484 729 #define LDCMRKRGBR 0xFE9404C4 730 #define LDCMRKCMYR 0xFE9404C8 731 #define LDCMRK1R 0xFE9404CC 732 #define LDCMRK2R 0xFE9404D0 733 #define LDCMGKRGBR 0xFE9404D4 734 #define LDCMGKCMYR 0xFE9404D8 735 #define LDCMGK1R 0xFE9404DC 736 #define LDCMGK2R 0xFE9404E0 737 #define LDCMBKRGBR 0xFE9404E4 738 #define LDCMBKCMYR 0xFE9404E8 739 #define LDCMBK1R 0xFE9404EC 740 #define LDCMBK2R 0xFE9404F0 741 #define LDCMHKPR 0xFE9404F4 742 #define LDCMHKQR 0xFE9404F8 743 #define LDCMSELR 0xFE9404FC 744 #define LDCMTVR 0xFE940500 745 #define LDCMTVSELR 0xFE940504 746 #define LDCMDTHR 0xFE940508 747 #define LDCMCNTR 0xFE94050C 748 #define SLDMT1R 0xFE940600 749 #define SLDMT2R 0xFE940604 750 #define SLDMT3R 0xFE940608 751 #define SLDDFR 0xFE94060C 752 #define SLDSM1R 0xFE940610 753 #define SLDSM2R 0xFE940614 754 #define SLDSA1R 0xFE940618 755 #define SLDSA2R 0xFE94061C 756 #define SLDMLSR 0xFE940620 757 #define SLDHCNR 0xFE940624 758 #define SLDHSYNR 0xFE940628 759 #define SLDVLNR 0xFE94062C 760 #define SLDVSYNR 0xFE940630 761 #define SLDHPDR 0xFE940634 762 #define SLDVPDR 0xFE940638 763 #define SLDPMR 0xFE94063C 764 #define LDDWD0R 0xFE940800 765 #define LDDWD1R 0xFE940804 766 #define LDDWD2R 0xFE940808 767 #define LDDWD3R 0xFE94080C 768 #define LDDWD4R 0xFE940810 769 #define LDDWD5R 0xFE940814 770 #define LDDWD6R 0xFE940818 771 #define LDDWD7R 0xFE94081C 772 #define LDDWD8R 0xFE940820 773 #define LDDWD9R 0xFE940824 774 #define LDDWDAR 0xFE940828 775 #define LDDWDBR 0xFE94082C 776 #define LDDWDCR 0xFE940830 777 #define LDDWDDR 0xFE940834 778 #define LDDWDER 0xFE940838 779 #define LDDWDFR 0xFE94083C 780 #define LDDRDR 0xFE940840 781 #define LDDWAR 0xFE940900 782 #define LDDRAR 0xFE940904 783 #define LDPR00 0xFE940000 784 785 /* VOU */ 786 #define VOUER 0xFE960000 787 #define VOUCR 0xFE960004 788 #define VOUSTR 0xFE960008 789 #define VOUVCR 0xFE96000C 790 #define VOUISR 0xFE960010 791 #define VOUBCR 0xFE960014 792 #define VOUDPR 0xFE960018 793 #define VOUDSR 0xFE96001C 794 #define VOUVPR 0xFE960020 795 #define VOUIR 0xFE960024 796 #define VOUSRR 0xFE960028 797 #define VOUMSR 0xFE96002C 798 #define VOUHIR 0xFE960030 799 #define VOUDFR 0xFE960034 800 #define VOUAD1R 0xFE960038 801 #define VOUAD2R 0xFE96003C 802 #define VOUAIR 0xFE960040 803 #define VOUSWR 0xFE960044 804 #define VOURCR 0xFE960048 805 #define VOURPR 0xFE960050 806 807 /* TSIF */ 808 #define TSCTLR 0xA4C80000 809 #define TSPIDR 0xA4C80004 810 #define TSCMDR 0xA4C80008 811 #define TSSTR 0xA4C8000C 812 #define TSTSDR 0xA4C80010 813 #define TSBUFCLRR 0xA4C80014 814 #define TSINTER 0xA4C80018 815 #define TSPSCALER 0xA4C80020 816 #define TSPSCALERR 0xA4C80024 817 #define TSPCRADCMDR 0xA4C80028 818 #define TSPCRADCR 0xA4C8002C 819 #define TSTRPCRADCR 0xA4C80030 820 #define TSDPCRADCR 0xA4C80034 821 822 /* SIU */ 823 #define IFCTL 0xA454C000 824 #define SRCTL 0xA454C004 825 #define SFORM 0xA454C008 826 #define CKCTL 0xA454C00C 827 #define TRDAT 0xA454C010 828 #define STFIFO 0xA454C014 829 #define DPAK 0xA454C01C 830 #define CKREV 0xA454C020 831 #define EVNTC 0xA454C028 832 #define SBCTL 0xA454C040 833 #define SBPSET 0xA454C044 834 #define SBBUS 0xA454C048 835 #define SBWFLG 0xA454C058 836 #define SBRFLG 0xA454C05C 837 #define SBWDAT 0xA454C060 838 #define SBRDAT 0xA454C064 839 #define SBFSTS 0xA454C068 840 #define SBDVCA 0xA454C06C 841 #define SBDVCB 0xA454C070 842 #define SBACTIV 0xA454C074 843 #define DMAIA 0xA454C090 844 #define DMAIB 0xA454C094 845 #define DMAOA 0xA454C098 846 #define DMAOB 0xA454C09C 847 #define SPLRI 0xA454C0B8 848 #define SPRRI 0xA454C0BC 849 #define SPURI 0xA454C0C4 850 #define SPTIS 0xA454C0C8 851 #define SPSTS 0xA454C0CC 852 #define SPCTL 0xA454C0D0 853 #define SPIRI 0xA454C0D4 854 #define SPQCF 0xA454C0D8 855 #define SPQCS 0xA454C0DC 856 #define SPQCT 0xA454C0E0 857 #define DPEAK 0xA454C0F0 858 #define DSLPD 0xA454C0F4 859 #define DSLLV 0xA454C0F8 860 #define BRGASEL 0xA454C100 861 #define BRRA 0xA454C104 862 #define BRGBSEL 0xA454C108 863 #define BRRB 0xA454C10C 864 865 /* USB */ 866 #define IFR0 0xA4480000 867 #define ISR0 0xA4480010 868 #define IER0 0xA4480020 869 #define EPDR0I 0xA4480030 870 #define EPDR0O 0xA4480034 871 #define EPDR0S 0xA4480038 872 #define EPDR1 0xA448003C 873 #define EPDR2 0xA4480040 874 #define EPDR3 0xA4480044 875 #define EPDR4 0xA4480048 876 #define EPDR5 0xA448004C 877 #define EPDR6 0xA4480050 878 #define EPDR7 0xA4480054 879 #define EPDR8 0xA4480058 880 #define EPDR9 0xA448005C 881 #define EPSZ0O 0xA4480080 882 #define EPSZ3 0xA4480084 883 #define EPSZ6 0xA4480088 884 #define EPSZ9 0xA448008C 885 #define TRG 0xA44800A0 886 #define DASTS 0xA44800A4 887 #define FCLR 0xA44800AA 888 #define DMA 0xA44800AC 889 #define EPSTL 0xA44800B2 890 #define CVR 0xA44800B4 891 #define TSR 0xA44800B8 892 #define CTLR 0xA44800BC 893 #define EPIR 0xA44800C0 894 #define XVERCR 0xA44800D0 895 #define STLMR 0xA44800D4 896 897 /* KEYSC */ 898 #define KYCR1 0xA44B0000 899 #define KYCR2 0xA44B0004 900 #define KYINDR 0xA44B0008 901 #define KYOUTDR 0xA44B000C 902 903 /* MMCIF */ 904 #define CMDR0 0xA4448000 905 #define CMDR1 0xA4448001 906 #define CMDR2 0xA4448002 907 #define CMDR3 0xA4448003 908 #define CMDR4 0xA4448004 909 #define CMDR5 0xA4448005 910 #define CMDSTRT 0xA4448006 911 #define OPCR 0xA444800A 912 #define CSTR 0xA444800B 913 #define INTCR0 0xA444800C 914 #define INTCR1 0xA444800D 915 #define INTSTR0 0xA444800E 916 #define INTSTR1 0xA444800F 917 #define CLKON 0xA4448010 918 #define CTOCR 0xA4448011 919 #define VDCNT 0xA4448012 920 #define TBCR 0xA4448014 921 #define MODER 0xA4448016 922 #define CMDTYR 0xA4448018 923 #define RSPTYR 0xA4448019 924 #define TBNCR 0xA444801A 925 #define RSPR0 0xA4448020 926 #define RSPR1 0xA4448021 927 #define RSPR2 0xA4448022 928 #define RSPR3 0xA4448023 929 #define RSPR4 0xA4448024 930 #define RSPR5 0xA4448025 931 #define RSPR6 0xA4448026 932 #define RSPR7 0xA4448027 933 #define RSPR8 0xA4448028 934 #define RSPR9 0xA4448029 935 #define RSPR10 0xA444802A 936 #define RSPR11 0xA444802B 937 #define RSPR12 0xA444802C 938 #define RSPR13 0xA444802D 939 #define RSPR14 0xA444802E 940 #define RSPR15 0xA444802F 941 #define RSPR16 0xA4448030 942 #define RSPRD 0xA4448031 943 #define DTOUTR 0xA4448032 944 #define DR 0xA4448040 945 #define FIFOCLR 0xA4448042 946 #define DMACR 0xA4448044 947 #define INTCR2 0xA4448046 948 #define INTSTR2 0xA4448048 949 950 /* Z3D3 */ 951 #define DLBI 0xFD980000 952 #define DLBD0 0xFD980080 953 #define DLBD1 0xFD980100 954 #define GEWM 0xFD984000 955 #define ICD0 0xFD988000 956 #define ICD1 0xFD989000 957 #define ICT 0xFD98A000 958 #define ILM 0xFD98C000 959 #define FLM0 0xFD98C800 960 #define FLM1 0xFD98D000 961 #define FLUT 0xFD98D800 962 #define Z3D_PC 0xFD98E400 963 #define Z3D_PCSP 0xFD98E404 964 #define Z3D_PAR 0xFD98E408 965 #define Z3D_IMADR 0xFD98E40C 966 #define Z3D_BTR0 0xFD98E410 967 #define Z3D_BTR1 0xFD98E414 968 #define Z3D_BTR2 0xFD98E418 969 #define Z3D_BTR3 0xFD98E41C 970 #define Z3D_LC0 0xFD98E420 971 #define Z3D_LC1 0xFD98E424 972 #define Z3D_LC2 0xFD98E428 973 #define Z3D_LC3 0xFD98E42C 974 #define Z3D_FR0 0xFD98E430 975 #define Z3D_FR1 0xFD98E434 976 #define Z3D_FR2 0xFD98E438 977 #define Z3D_SR 0xFD98E440 978 #define Z3D_SMDR 0xFD98E444 979 #define Z3D_PBIR 0xFD98E448 980 #define Z3D_DMDR 0xFD98E44C 981 #define Z3D_IREG 0xFD98E460 982 #define Z3D_AR00 0xFD98E480 983 #define Z3D_AR01 0xFD98E484 984 #define Z3D_AR02 0xFD98E488 985 #define Z3D_AR03 0xFD98E48C 986 #define Z3D_BR00 0xFD98E490 987 #define Z3D_BR01 0xFD98E494 988 #define Z3D_IXR00 0xFD98E4A0 989 #define Z3D_IXR01 0xFD98E4A4 990 #define Z3D_IXR02 0xFD98E4A8 991 #define Z3D_IXR03 0xFD98E4AC 992 #define Z3D_AR10 0xFD98E4C0 993 #define Z3D_AR11 0xFD98E4C4 994 #define Z3D_AR12 0xFD98E4C8 995 #define Z3D_AR13 0xFD98E4CC 996 #define Z3D_BR10 0xFD98E4D0 997 #define Z3D_BR11 0xFD98E4D4 998 #define Z3D_IXR10 0xFD98E4E0 999 #define Z3D_IXR11 0xFD98E4E4 1000 #define Z3D_IXR12 0xFD98E4E8 1001 #define Z3D_IXR13 0xFD98E4EC 1002 #define Z3D_AR20 0xFD98E500 1003 #define Z3D_AR21 0xFD98E504 1004 #define Z3D_AR22 0xFD98E508 1005 #define Z3D_AR23 0xFD98E50C 1006 #define Z3D_BR20 0xFD98E510 1007 #define Z3D_BR21 0xFD98E514 1008 #define Z3D_IXR20 0xFD98E520 1009 #define Z3D_IXR21 0xFD98E524 1010 #define Z3D_IXR22 0xFD98E528 1011 #define Z3D_IXR23 0xFD98E52C 1012 #define Z3D_MR0 0xFD98E540 1013 #define Z3D_MR1 0xFD98E544 1014 #define Z3D_MR2 0xFD98E548 1015 #define Z3D_MR3 0xFD98E54C 1016 #define Z3D_WORKRST 0xFD98E558 1017 #define Z3D_WORKWST 0xFD98E55C 1018 #define Z3D_DBADR 0xFD98E560 1019 #define Z3D_DLBPRST 0xFD98E564 1020 #define Z3D_DLBRST 0xFD98E568 1021 #define Z3D_DLBWST 0xFD98E56C 1022 #define Z3D_UDR0 0xFD98E570 1023 #define Z3D_UDR1 0xFD98E574 1024 #define Z3D_UDR2 0xFD98E578 1025 #define Z3D_UDR3 0xFD98E57C 1026 #define Z3D_CCR0 0xFD98E580 1027 #define Z3D_CCR1 0xFD98E584 1028 #define Z3D_EXPR 0xFD98E588 1029 #define Z3D_V0_X 0xFD9A0000 1030 #define Z3D_V0_Y 0xFD9A0004 1031 #define Z3D_V0_Z 0xFD9A0008 1032 #define Z3D_V0_W 0xFD9A000C 1033 #define Z3D_V0_A 0xFD9A0010 1034 #define Z3D_V0_R 0xFD9A0014 1035 #define Z3D_V0_G 0xFD9A0018 1036 #define Z3D_V0_B 0xFD9A001C 1037 #define Z3D_V0_F 0xFD9A0020 1038 #define Z3D_V0_SR 0xFD9A0024 1039 #define Z3D_V0_SG 0xFD9A0028 1040 #define Z3D_V0_SB 0xFD9A002C 1041 #define Z3D_V0_U0 0xFD9A0030 1042 #define Z3D_V0_V0 0xFD9A0034 1043 #define Z3D_V0_U1 0xFD9A0038 1044 #define Z3D_V0_V1 0xFD9A003C 1045 #define Z3D_V1_X 0xFD9A0080 1046 #define Z3D_V1_Y 0xFD9A0084 1047 #define Z3D_V1_Z 0xFD9A0088 1048 #define Z3D_V1_W 0xFD9A008C 1049 #define Z3D_V1_A 0xFD9A0090 1050 #define Z3D_V1_R 0xFD9A0094 1051 #define Z3D_V1_G 0xFD9A0098 1052 #define Z3D_V1_B 0xFD9A009C 1053 #define Z3D_V1_F 0xFD9A00A0 1054 #define Z3D_V1_SR 0xFD9A00A4 1055 #define Z3D_V1_SG 0xFD9A00A8 1056 #define Z3D_V1_SB 0xFD9A00AC 1057 #define Z3D_V1_U0 0xFD9A00B0 1058 #define Z3D_V1_V0 0xFD9A00B4 1059 #define Z3D_V1_U1 0xFD9A00B8 1060 #define Z3D_V1_V1 0xFD9A00BC 1061 #define Z3D_V2_X 0xFD9A0100 1062 #define Z3D_V2_Y 0xFD9A0104 1063 #define Z3D_V2_Z 0xFD9A0108 1064 #define Z3D_V2_W 0xFD9A010C 1065 #define Z3D_V2_A 0xFD9A0110 1066 #define Z3D_V2_R 0xFD9A0114 1067 #define Z3D_V2_G 0xFD9A0118 1068 #define Z3D_V2_B 0xFD9A011C 1069 #define Z3D_V2_F 0xFD9A0120 1070 #define Z3D_V2_SR 0xFD9A0124 1071 #define Z3D_V2_SG 0xFD9A0128 1072 #define Z3D_V2_SB 0xFD9A012C 1073 #define Z3D_V2_U0 0xFD9A0130 1074 #define Z3D_V2_V0 0xFD9A0134 1075 #define Z3D_V2_U1 0xFD9A0138 1076 #define Z3D_V2_V1 0xFD9A013C 1077 #define Z3D_RENDER 0xFD9A0180 1078 #define Z3D_POLYGON_OFFSET 0xFD9A0184 1079 #define Z3D_VERTEX_CONTROL 0xFD9A0200 1080 #define Z3D_STATE_MODE 0xFD9A0204 1081 #define Z3D_FPU_MODE 0xFD9A0318 1082 #define Z3D_SCISSOR_MIN 0xFD9A0400 1083 #define Z3D_SCISSOR_MAX 0xFD9A0404 1084 #define Z3D_TEXTURE_MODE_A 0xFD9A0408 1085 #define Z3D_TEXTURE_MODE_B 0xFD9A040C 1086 #define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 1087 #define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C 1088 #define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 1089 #define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 1090 #define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 1091 #define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C 1092 #define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 1093 #define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 1094 #define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 1095 #define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C 1096 #define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 1097 #define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 1098 #define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 1099 #define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C 1100 #define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 1101 #define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 1102 #define Z3D_TEXTURE_FLUSH 0xFD9A0498 1103 #define Z3D_GAMMA_TABLE0 0xFD9A049C 1104 #define Z3D_GAMMA_TABLE1 0xFD9A04A0 1105 #define Z3D_GAMMA_TABLE2 0xFD9A04A4 1106 #define Z3D_ALPHA_TEST 0xFD9A0800 1107 #define Z3D_STENCIL_TEST 0xFD9A0804 1108 #define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 1109 #define Z3D_MASK 0xFD9A080C 1110 #define Z3D_FBUS_MODE 0xFD9A0810 1111 #define Z3D_GNT_SET 0xFD9A0814 1112 #define Z3D_BETWEEN_TEST 0xFD9A0818 1113 #define Z3D_FB_BASE 0xFD9A081C 1114 #define Z3D_LCD_SIZE 0xFD9A0820 1115 #define Z3D_FB_FLUSH 0xFD9A0824 1116 #define Z3D_CACHE_INVALID 0xFD9A0828 1117 #define Z3D_SC_MODE 0xFD9A0830 1118 #define Z3D_SC0_MIN 0xFD9A0834 1119 #define Z3D_SC0_MAX 0xFD9A0838 1120 #define Z3D_SC1_MIN 0xFD9A083C 1121 #define Z3D_SC1_MAX 0xFD9A0840 1122 #define Z3D_SC2_MIN 0xFD9A0844 1123 #define Z3D_SC2_MAX 0xFD9A0848 1124 #define Z3D_SC3_MIN 0xFD9A084C 1125 #define Z3D_SC3_MAX 0xFD9A0850 1126 #define Z3D_READRESET 0xFD9A0854 1127 #define Z3D_DET_MIN 0xFD9A0858 1128 #define Z3D_DET_MAX 0xFD9A085C 1129 #define Z3D_FB_BASE_SR 0xFD9A0860 1130 #define Z3D_LCD_SIZE_SR 0xFD9A0864 1131 #define Z3D_2D_CTRL_STATUS 0xFD9A0C00 1132 #define Z3D_2D_SIZE 0xFD9A0C04 1133 #define Z3D_2D_SRCLOC 0xFD9A0C08 1134 #define Z3D_2D_DSTLOC 0xFD9A0C0C 1135 #define Z3D_2D_DMAPORT 0xFD9A0C10 1136 #define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 1137 #define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 1138 #define Z3D_2D_STPCOLOR0 0xFD9A0C1C 1139 #define Z3D_2D_STPCOLOR1 0xFD9A0C20 1140 #define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 1141 #define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 1142 #define Z3D_2D_STPPAT_0 0xFD9A0C40 1143 #define Z3D_2D_STPPAT_1 0xFD9A0C44 1144 #define Z3D_2D_STPPAT_2 0xFD9A0C48 1145 #define Z3D_2D_STPPAT_3 0xFD9A0C4C 1146 #define Z3D_2D_STPPAT_4 0xFD9A0C50 1147 #define Z3D_2D_STPPAT_5 0xFD9A0C54 1148 #define Z3D_2D_STPPAT_6 0xFD9A0C58 1149 #define Z3D_2D_STPPAT_7 0xFD9A0C5C 1150 #define Z3D_2D_STPPAT_8 0xFD9A0C60 1151 #define Z3D_2D_STPPAT_9 0xFD9A0C64 1152 #define Z3D_2D_STPPAT_10 0xFD9A0C68 1153 #define Z3D_2D_STPPAT_11 0xFD9A0C6C 1154 #define Z3D_2D_STPPAT_12 0xFD9A0C70 1155 #define Z3D_2D_STPPAT_13 0xFD9A0C74 1156 #define Z3D_2D_STPPAT_14 0xFD9A0C78 1157 #define Z3D_2D_STPPAT_15 0xFD9A0C7C 1158 #define Z3D_2D_STPPAT_16 0xFD9A0C80 1159 #define Z3D_2D_STPPAT_17 0xFD9A0C84 1160 #define Z3D_2D_STPPAT_18 0xFD9A0C88 1161 #define Z3D_2D_STPPAT_19 0xFD9A0C8C 1162 #define Z3D_2D_STPPAT_20 0xFD9A0C90 1163 #define Z3D_2D_STPPAT_21 0xFD9A0C94 1164 #define Z3D_2D_STPPAT_22 0xFD9A0C98 1165 #define Z3D_2D_STPPAT_23 0xFD9A0C9C 1166 #define Z3D_2D_STPPAT_24 0xFD9A0CA0 1167 #define Z3D_2D_STPPAT_25 0xFD9A0CA4 1168 #define Z3D_2D_STPPAT_26 0xFD9A0CA8 1169 #define Z3D_2D_STPPAT_27 0xFD9A0CAC 1170 #define Z3D_2D_STPPAT_28 0xFD9A0CB0 1171 #define Z3D_2D_STPPAT_29 0xFD9A0CB4 1172 #define Z3D_2D_STPPAT_30 0xFD9A0CB8 1173 #define Z3D_2D_STPPAT_31 0xFD9A0CBC 1174 #define Z3D_WR_CTRL 0xFD9A1000 1175 #define Z3D_WR_P0 0xFD9A1004 1176 #define Z3D_WR_P1 0xFD9A1008 1177 #define Z3D_WR_P2 0xFD9A100C 1178 #define Z3D_WR_FGC 0xFD9A1010 1179 #define Z3D_WR_BGC 0xFD9A1014 1180 #define Z3D_WR_SZ 0xFD9A1018 1181 #define Z3D_WR_PATPARAM 0xFD9A101C 1182 #define Z3D_WR_PAT 0xFD9A1020 1183 #define Z3D_SYS_STATUS 0xFD9A1400 1184 #define Z3D_SYS_RESET 0xFD9A1404 1185 #define Z3D_SYS_CLK 0xFD9A1408 1186 #define Z3D_SYS_CONF 0xFD9A140C 1187 #define Z3D_SYS_VERSION 0xFD9A1410 1188 #define Z3D_SYS_DBINV 0xFD9A1418 1189 #define Z3D_SYS_I2F_FMT 0xFD9A1420 1190 #define Z3D_SYS_I2F_SRC 0xFD9A1424 1191 #define Z3D_SYS_I2F_DST 0xFD9A1428 1192 #define Z3D_SYS_GBCNT 0xFD9A1430 1193 #define Z3D_SYS_BSYCNT 0xFD9A1434 1194 #define Z3D_SYS_INT_STATUS 0xFD9A1450 1195 #define Z3D_SYS_INT_MASK 0xFD9A1454 1196 #define Z3D_SYS_INT_CLEAR 0xFD9A1458 1197 #define TCD0 0xFD9C0000 1198 #define TCD1 0xFD9C0400 1199 #define TCD2 0xFD9C0800 1200 #define TCD3 0xFD9C0C00 1201 #define TCT0 0xFD9C1000 1202 #define TCT1 0xFD9C1400 1203 #define TCT2 0xFD9C1800 1204 #define TCT3 0xFD9C1C00 1205 1206 /* PFC */ 1207 #define PACR 0xA4050100 1208 #define PBCR 0xA4050102 1209 #define PCCR 0xA4050104 1210 #define PDCR 0xA4050106 1211 #define PECR 0xA4050108 1212 #define PFCR 0xA405010A 1213 #define PGCR 0xA405010C 1214 #define PHCR 0xA405010E 1215 #define PJCR 0xA4050110 1216 #define PKCR 0xA4050112 1217 #define PLCR 0xA4050114 1218 #define PMCR 0xA4050116 1219 #define PNCR 0xA4050118 1220 #define PQCR 0xA405011A 1221 #define PRCR 0xA405011C 1222 #define PSCR 0xA405011E 1223 #define PTCR 0xA4050140 1224 #define PUCR 0xA4050142 1225 #define PVCR 0xA4050144 1226 #define PWCR 0xA4050146 1227 #define PXCR 0xA4050148 1228 #define PYCR 0xA405014A 1229 #define PZCR 0xA405014C 1230 #define PSELA 0xA405014E 1231 #define PSELB 0xA4050150 1232 #define PSELC 0xA4050152 1233 #define PSELD 0xA4050154 1234 #define PSELE 0xA4050156 1235 #define HIZCRA 0xA4050158 1236 #define HIZCRB 0xA405015A 1237 #define HIZCRC 0xA405015C 1238 #define HIZCRC 0xA405015C 1239 #define MSELCRA 0xA4050180 1240 #define MSELCRB 0xA4050182 1241 #define PULCR 0xA4050184 1242 #define SBSCR 0xA4050186 1243 #define DRVCR 0xA405018A 1244 1245 /* I/O Port */ 1246 #define PADR 0xA4050120 1247 #define PBDR 0xA4050122 1248 #define PCDR 0xA4050124 1249 #define PDDR 0xA4050126 1250 #define PEDR 0xA4050128 1251 #define PFDR 0xA405012A 1252 #define PGDR 0xA405012C 1253 #define PHDR 0xA405012E 1254 #define PJDR 0xA4050130 1255 #define PKDR 0xA4050132 1256 #define PLDR 0xA4050134 1257 #define PMDR 0xA4050136 1258 #define PNDR 0xA4050138 1259 #define PQDR 0xA405013A 1260 #define PRDR 0xA405013C 1261 #define PSDR 0xA405013E 1262 #define PTDR 0xA4050160 1263 #define PUDR 0xA4050162 1264 #define PVDR 0xA4050164 1265 #define PWDR 0xA4050166 1266 #define PYDR 0xA4050168 1267 #define PZDR 0xA405016A 1268 1269 /* UBC */ 1270 #define CBR0 0xFF200000 1271 #define CRR0 0xFF200004 1272 #define CAR0 0xFF200008 1273 #define CAMR0 0xFF20000C 1274 #define CBR1 0xFF200020 1275 #define CRR1 0xFF200024 1276 #define CAR1 0xFF200028 1277 #define CAMR1 0xFF20002C 1278 #define CDR1 0xFF200030 1279 #define CDMR1 0xFF200034 1280 #define CETR1 0xFF200038 1281 #define CCMFR 0xFF200600 1282 #define CBCR 0xFF200620 1283 1284 /* H-UDI */ 1285 #define SDIR 0xFC110000 1286 #define SDDRH 0xFC110008 1287 #define SDDRL 0xFC11000A 1288 #define SDINT 0xFC110018 1289 1290 #endif /* _ASM_CPU_SH7722_H_ */ 1291