1 /* 2 * Copyright 2007 (C) 3 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 4 * 5 * Copyright 2008 (C) 6 * Mark Jonas <mark.jonas@de.bosch.com> 7 * 8 * SH7720 Internal I/O register 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef _ASM_CPU_SH7720_H_ 27 #define _ASM_CPU_SH7720_H_ 28 29 #define CACHE_OC_NUM_WAYS 4 30 #define CCR_CACHE_INIT 0x0000000B 31 32 /* EXP */ 33 #define TRA 0xFFFFFFD0 34 #define EXPEVT 0xFFFFFFD4 35 #define INTEVT 0xFFFFFFD8 36 37 /* MMU */ 38 #define MMUCR 0xFFFFFFE0 39 #define PTEH 0xFFFFFFF0 40 #define PTEL 0xFFFFFFF4 41 #define TTB 0xFFFFFFF8 42 43 /* CACHE */ 44 #define CCR 0xFFFFFFEC 45 46 /* INTC */ 47 #define IPRF 0xA4080000 48 #define IPRG 0xA4080002 49 #define IPRH 0xA4080004 50 #define IPRI 0xA4080006 51 #define IPRJ 0xA4080008 52 #define IRR5 0xA4080020 53 #define IRR6 0xA4080022 54 #define IRR7 0xA4080024 55 #define IRR8 0xA4080026 56 #define IRR9 0xA4080028 57 #define IRR0 0xA4140004 58 #define IRR1 0xA4140006 59 #define IRR2 0xA4140008 60 #define IRR3 0xA414000A 61 #define IRR4 0xA414000C 62 #define ICR1 0xA4140010 63 #define ICR2 0xA4140012 64 #define PINTER 0xA4140014 65 #define IPRC 0xA4140016 66 #define IPRD 0xA4140018 67 #define IPRE 0xA414001A 68 #define ICR0 0xA414FEE0 69 #define IPRA 0xA414FEE2 70 #define IPRB 0xA414FEE4 71 72 /* BSC */ 73 #define BSC_BASE 0xA4FD0000 74 #define CMNCR (BSC_BASE + 0x00) 75 #define CS0BCR (BSC_BASE + 0x04) 76 #define CS2BCR (BSC_BASE + 0x08) 77 #define CS3BCR (BSC_BASE + 0x0C) 78 #define CS4BCR (BSC_BASE + 0x10) 79 #define CS5ABCR (BSC_BASE + 0x14) 80 #define CS5BBCR (BSC_BASE + 0x18) 81 #define CS6ABCR (BSC_BASE + 0x1C) 82 #define CS6BBCR (BSC_BASE + 0x20) 83 #define CS0WCR (BSC_BASE + 0x24) 84 #define CS2WCR (BSC_BASE + 0x28) 85 #define CS3WCR (BSC_BASE + 0x2C) 86 #define CS4WCR (BSC_BASE + 0x30) 87 #define CS5AWCR (BSC_BASE + 0x34) 88 #define CS5BWCR (BSC_BASE + 0x38) 89 #define CS6AWCR (BSC_BASE + 0x3C) 90 #define CS6BWCR (BSC_BASE + 0x40) 91 #define SDCR (BSC_BASE + 0x44) 92 #define RTCSR (BSC_BASE + 0x48) 93 #define RTCNR (BSC_BASE + 0x4C) 94 #define RTCOR (BSC_BASE + 0x50) 95 #define SDMR2 (BSC_BASE + 0x4000) 96 #define SDMR3 (BSC_BASE + 0x5000) 97 98 /* DMAC */ 99 100 /* CPG */ 101 #define UCLKCR 0xA40A0008 102 #define FRQCR 0xA415FF80 103 104 /* LOW POWER MODE */ 105 106 /* TMU */ 107 #define TMU_BASE 0xA412FE90 108 109 /* TPU */ 110 #define TPU_BASE 0xA4480000 111 #define TPU_TSTR (TPU_BASE + 0x00) 112 #define TPU_TCR0 (TPU_BASE + 0x10) 113 #define TPU_TMDR0 (TPU_BASE + 0x14) 114 #define TPU_TIOR0 (TPU_BASE + 0x18) 115 #define TPU_TIER0 (TPU_BASE + 0x1C) 116 #define TPU_TSR0 (TPU_BASE + 0x20) 117 #define TPU_TCNT0 (TPU_BASE + 0x24) 118 #define TPU_TGRA0 (TPU_BASE + 0x28) 119 #define TPU_TGRB0 (TPU_BASE + 0x2C) 120 #define TPU_TGRC0 (TPU_BASE + 0x30) 121 #define TPU_TGRD0 (TPU_BASE + 0x34) 122 #define TPU_TCR1 (TPU_BASE + 0x50) 123 #define TPU_TMDR1 (TPU_BASE + 0x54) 124 #define TPU_TIOR1 (TPU_BASE + 0x58) 125 #define TPU_TIER1 (TPU_BASE + 0x5C) 126 #define TPU_TSR1 (TPU_BASE + 0x60) 127 #define TPU_TCNT1 (TPU_BASE + 0x64) 128 #define TPU_TGRA1 (TPU_BASE + 0x68) 129 #define TPU_TGRB1 (TPU_BASE + 0x6C) 130 #define TPU_TGRC1 (TPU_BASE + 0x70) 131 #define TPU_TGRD1 (TPU_BASE + 0x74) 132 #define TPU_TCR2 (TPU_BASE + 0x90) 133 #define TPU_TMDR2 (TPU_BASE + 0x94) 134 #define TPU_TIOR2 (TPU_BASE + 0x98) 135 #define TPU_TIER2 (TPU_BASE + 0x9C) 136 #define TPU_TSR2 (TPU_BASE + 0xB0) 137 #define TPU_TCNT2 (TPU_BASE + 0xB4) 138 #define TPU_TGRA2 (TPU_BASE + 0xB8) 139 #define TPU_TGRB2 (TPU_BASE + 0xBC) 140 #define TPU_TGRC2 (TPU_BASE + 0xC0) 141 #define TPU_TGRD2 (TPU_BASE + 0xC4) 142 #define TPU_TCR3 (TPU_BASE + 0xD0) 143 #define TPU_TMDR3 (TPU_BASE + 0xD4) 144 #define TPU_TIOR3 (TPU_BASE + 0xD8) 145 #define TPU_TIER3 (TPU_BASE + 0xDC) 146 #define TPU_TSR3 (TPU_BASE + 0xE0) 147 #define TPU_TCNT3 (TPU_BASE + 0xE4) 148 #define TPU_TGRA3 (TPU_BASE + 0xE8) 149 #define TPU_TGRB3 (TPU_BASE + 0xEC) 150 #define TPU_TGRC3 (TPU_BASE + 0xF0) 151 #define TPU_TGRD3 (TPU_BASE + 0xF4) 152 153 /* CMT */ 154 155 /* SIOF */ 156 157 /* SCIF */ 158 #define SCIF0_BASE 0xA4430000 159 160 /* SIM */ 161 162 /* IrDA */ 163 164 /* IIC */ 165 166 /* LCDC */ 167 168 /* USBF */ 169 170 /* MMCIF */ 171 172 /* PFC */ 173 #define PFC_BASE 0xA4050100 174 #define PACR (PFC_BASE + 0x00) 175 #define PBCR (PFC_BASE + 0x02) 176 #define PCCR (PFC_BASE + 0x04) 177 #define PDCR (PFC_BASE + 0x06) 178 #define PECR (PFC_BASE + 0x08) 179 #define PFCR (PFC_BASE + 0x0A) 180 #define PGCR (PFC_BASE + 0x0C) 181 #define PHCR (PFC_BASE + 0x0E) 182 #define PJCR (PFC_BASE + 0x10) 183 #define PKCR (PFC_BASE + 0x12) 184 #define PLCR (PFC_BASE + 0x14) 185 #define PMCR (PFC_BASE + 0x16) 186 #define PPCR (PFC_BASE + 0x18) 187 #define PRCR (PFC_BASE + 0x1A) 188 #define PSCR (PFC_BASE + 0x1C) 189 #define PTCR (PFC_BASE + 0x1E) 190 #define PUCR (PFC_BASE + 0x20) 191 #define PVCR (PFC_BASE + 0x22) 192 #define PSELA (PFC_BASE + 0x24) 193 #define PSELB (PFC_BASE + 0x26) 194 #define PSELC (PFC_BASE + 0x28) 195 #define PSELD (PFC_BASE + 0x2A) 196 197 /* I/O Port */ 198 #define PORT_BASE 0xA4050100 199 #define PADR (PORT_BASE + 0x40) 200 #define PBDR (PORT_BASE + 0x42) 201 #define PCDR (PORT_BASE + 0x44) 202 #define PDDR (PORT_BASE + 0x46) 203 #define PEDR (PORT_BASE + 0x48) 204 #define PFDR (PORT_BASE + 0x4A) 205 #define PGDR (PORT_BASE + 0x4C) 206 #define PHDR (PORT_BASE + 0x4E) 207 #define PJDR (PORT_BASE + 0x50) 208 #define PKDR (PORT_BASE + 0x52) 209 #define PLDR (PORT_BASE + 0x54) 210 #define PMDR (PORT_BASE + 0x56) 211 #define PPDR (PORT_BASE + 0x58) 212 #define PRDR (PORT_BASE + 0x5A) 213 #define PSDR (PORT_BASE + 0x5C) 214 #define PTDR (PORT_BASE + 0x5E) 215 #define PUDR (PORT_BASE + 0x60) 216 #define PVDR (PORT_BASE + 0x62) 217 218 /* H-UDI */ 219 220 #endif /* _ASM_CPU_SH7720_H_ */ 221