1 /* 2 * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef _ASM_CPU_SH4_H_ 21 #define _ASM_CPU_SH4_H_ 22 23 /* cache control */ 24 #define CCR_CACHE_STOP 0x00000808 25 #define CCR_CACHE_ENABLE 0x00000101 26 #define CCR_CACHE_ICI 0x00000800 27 28 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 29 30 #if defined (CONFIG_CPU_SH7750) || \ 31 defined(CONFIG_CPU_SH7751) 32 #define CACHE_OC_WAY_SHIFT 14 33 #define CACHE_OC_NUM_ENTRIES 512 34 #else 35 #define CACHE_OC_WAY_SHIFT 13 36 #define CACHE_OC_NUM_ENTRIES 256 37 #endif 38 #define CACHE_OC_ENTRY_SHIFT 5 39 40 #if defined (CONFIG_CPU_SH7750) || \ 41 defined(CONFIG_CPU_SH7751) 42 # include <asm/cpu_sh7750.h> 43 #elif defined (CONFIG_CPU_SH7722) 44 # include <asm/cpu_sh7722.h> 45 #elif defined (CONFIG_CPU_SH7723) 46 # include <asm/cpu_sh7723.h> 47 #elif defined (CONFIG_CPU_SH7724) 48 # include <asm/cpu_sh7724.h> 49 #elif defined (CONFIG_CPU_SH7757) 50 # include <asm/cpu_sh7757.h> 51 #elif defined (CONFIG_CPU_SH7763) 52 # include <asm/cpu_sh7763.h> 53 #elif defined (CONFIG_CPU_SH7780) 54 # include <asm/cpu_sh7780.h> 55 #elif defined (CONFIG_CPU_SH7785) 56 # include <asm/cpu_sh7785.h> 57 #else 58 # error "Unknown SH4 variant" 59 #endif 60 61 #if defined(CONFIG_SH_32BIT) 62 #define PMB_ADDR_ARRAY 0xf6100000 63 #define PMB_ADDR_ENTRY 8 64 #define PMB_VPN 24 65 66 #define PMB_DATA_ARRAY 0xf7100000 67 #define PMB_DATA_ENTRY 8 68 #define PMB_PPN 24 69 #define PMB_UB 9 /* Buffered write */ 70 #define PMB_V 8 /* Valid */ 71 #define PMB_SZ1 7 /* Page size (upper bit) */ 72 #define PMB_SZ0 4 /* Page size (lower bit) */ 73 #define PMB_C 3 /* Cacheability */ 74 #define PMB_WT 0 /* Write-through */ 75 76 #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) 77 #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) 78 #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) 79 #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ 80 ((ppn << PMB_PPN) | (ub << PMB_UB) | \ 81 (v << PMB_V) | (sz1 << PMB_SZ1) | \ 82 (sz0 << PMB_SZ0) | (c << PMB_C) | \ 83 (wt << PMB_WT)) 84 #endif 85 86 #endif /* _ASM_CPU_SH4_H_ */ 87