1 #ifndef __ASM_SH_CACHE_H 2 #define __ASM_SH_CACHE_H 3 4 #if defined(CONFIG_CPU_SH4) 5 6 #define L1_CACHE_BYTES 32 7 8 struct __large_struct { unsigned long buf[100]; }; 9 #define __m(x) (*(struct __large_struct *)(x)) 10 11 #else 12 13 /* 14 * 32-bytes is the largest L1 data cache line size for SH the architecture. So 15 * it is a safe default for DMA alignment. 16 */ 17 #define ARCH_DMA_MINALIGN 32 18 19 #endif /* CONFIG_CPU_SH4 */ 20 21 /* 22 * Use the L1 data cache line size value for the minimum DMA buffer alignment 23 * on SH. 24 */ 25 #ifndef ARCH_DMA_MINALIGN 26 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 27 #endif 28 29 #endif /* __ASM_SH_CACHE_H */ 30