1 #ifndef __ASM_SH_CACHE_H 2 #define __ASM_SH_CACHE_H 3 4 #if defined(CONFIG_CPU_SH4) 5 6 int cache_control(unsigned int cmd); 7 8 #define L1_CACHE_BYTES 32 9 10 struct __large_struct { unsigned long buf[100]; }; 11 #define __m(x) (*(struct __large_struct *)(x)) 12 13 #else 14 15 /* 16 * 32-bytes is the largest L1 data cache line size for SH the architecture. So 17 * it is a safe default for DMA alignment. 18 */ 19 #define ARCH_DMA_MINALIGN 32 20 21 #endif /* CONFIG_CPU_SH4 */ 22 23 /* 24 * Use the L1 data cache line size value for the minimum DMA buffer alignment 25 * on SH. 26 */ 27 #ifndef ARCH_DMA_MINALIGN 28 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 29 #endif 30 31 #endif /* __ASM_SH_CACHE_H */ 32