1*c7ba7bdcSDan Murphy /* 2*c7ba7bdcSDan Murphy * TI DP83867 PHY drivers 3*c7ba7bdcSDan Murphy * 4*c7ba7bdcSDan Murphy * SPDX-License-Identifier: GPL-2.0 5*c7ba7bdcSDan Murphy * 6*c7ba7bdcSDan Murphy */ 7*c7ba7bdcSDan Murphy 8*c7ba7bdcSDan Murphy #ifndef _DT_BINDINGS_TI_DP83867_H 9*c7ba7bdcSDan Murphy #define _DT_BINDINGS_TI_DP83867_H 10*c7ba7bdcSDan Murphy 11*c7ba7bdcSDan Murphy /* PHY CTRL bits */ 12*c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 13*c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 14*c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 15*c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 16*c7ba7bdcSDan Murphy 17*c7ba7bdcSDan Murphy /* RGMIIDCTL internal delay for rx and tx */ 18*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_250_PS 0x0 19*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_500_PS 0x1 20*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_750_PS 0x2 21*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_NS 0x3 22*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_25_NS 0x4 23*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_50_NS 0x5 24*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_75_NS 0x6 25*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_00_NS 0x7 26*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_25_NS 0x8 27*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_50_NS 0x9 28*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_75_NS 0xa 29*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_00_NS 0xb 30*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_25_NS 0xc 31*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_50_NS 0xd 32*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_75_NS 0xe 33*c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_4_00_NS 0xf 34*c7ba7bdcSDan Murphy 35*c7ba7bdcSDan Murphy #endif 36