1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2c7ba7bdcSDan Murphy /* 3c7ba7bdcSDan Murphy * TI DP83867 PHY drivers 4c7ba7bdcSDan Murphy * 5c7ba7bdcSDan Murphy */ 6c7ba7bdcSDan Murphy 7c7ba7bdcSDan Murphy #ifndef _DT_BINDINGS_TI_DP83867_H 8c7ba7bdcSDan Murphy #define _DT_BINDINGS_TI_DP83867_H 9c7ba7bdcSDan Murphy 10c7ba7bdcSDan Murphy /* PHY CTRL bits */ 11c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 12c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 13c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 14c7ba7bdcSDan Murphy #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 15c7ba7bdcSDan Murphy 16c7ba7bdcSDan Murphy /* RGMIIDCTL internal delay for rx and tx */ 17c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_250_PS 0x0 18c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_500_PS 0x1 19c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_750_PS 0x2 20c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_NS 0x3 21c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_25_NS 0x4 22c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_50_NS 0x5 23c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_1_75_NS 0x6 24c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_00_NS 0x7 25c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_25_NS 0x8 26c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_50_NS 0x9 27c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_2_75_NS 0xa 28c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_00_NS 0xb 29c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_25_NS 0xc 30c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_50_NS 0xd 31c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_3_75_NS 0xe 32c7ba7bdcSDan Murphy #define DP83867_RGMIIDCTL_4_00_NS 0xf 33c7ba7bdcSDan Murphy 34c7ba7bdcSDan Murphy #endif 35