16c9a1003SVikas Manocha #ifndef DT_BINDINGS_STM32_SDRAM_H 26c9a1003SVikas Manocha #define DT_BINDINGS_STM32_SDRAM_H 36c9a1003SVikas Manocha 46c9a1003SVikas Manocha #define NO_COL_8 0x0 56c9a1003SVikas Manocha #define NO_COL_9 0x1 66c9a1003SVikas Manocha #define NO_COL_10 0x2 76c9a1003SVikas Manocha #define NO_COL_11 0x3 86c9a1003SVikas Manocha 96c9a1003SVikas Manocha #define NO_ROW_11 0x0 106c9a1003SVikas Manocha #define NO_ROW_12 0x1 116c9a1003SVikas Manocha #define NO_ROW_13 0x2 126c9a1003SVikas Manocha 136c9a1003SVikas Manocha #define MWIDTH_8 0x0 146c9a1003SVikas Manocha #define MWIDTH_16 0x1 156c9a1003SVikas Manocha #define MWIDTH_32 0x2 166c9a1003SVikas Manocha #define BANKS_2 0x0 176c9a1003SVikas Manocha #define BANKS_4 0x1 186c9a1003SVikas Manocha #define CAS_1 0x1 196c9a1003SVikas Manocha #define CAS_2 0x2 206c9a1003SVikas Manocha #define CAS_3 0x3 21*bfea69adSVikas Manocha #define SDCLK_2 0x2 226c9a1003SVikas Manocha #define RD_BURST_EN 0x1 236c9a1003SVikas Manocha #define RD_BURST_DIS 0x0 246c9a1003SVikas Manocha #define RD_PIPE_DL_0 0x0 256c9a1003SVikas Manocha #define RD_PIPE_DL_1 0x1 266c9a1003SVikas Manocha #define RD_PIPE_DL_2 0x2 276c9a1003SVikas Manocha 28*bfea69adSVikas Manocha /* Timing = value +1 cycles */ 29*bfea69adSVikas Manocha #define TMRD_2 (2 - 1) 30*bfea69adSVikas Manocha #define TXSR_6 (6 - 1) 31*bfea69adSVikas Manocha #define TRAS_4 (4 - 1) 32*bfea69adSVikas Manocha #define TRC_6 (6 - 1) 33*bfea69adSVikas Manocha #define TWR_2 (2 - 1) 34*bfea69adSVikas Manocha #define TRP_2 (2 - 1) 35*bfea69adSVikas Manocha #define TRCD_2 (2 - 1) 366c9a1003SVikas Manocha 376c9a1003SVikas Manocha #endif 38