1*c40b6df8SAnup Patel /* SPDX-License-Identifier: GPL-2.0 */ 2*c40b6df8SAnup Patel /* 3*c40b6df8SAnup Patel * Copyright (c) 2019 Western Digital Corporation or its affiliates. 4*c40b6df8SAnup Patel * 5*c40b6df8SAnup Patel * Copyright (C) 2018 SiFive, Inc. 6*c40b6df8SAnup Patel * Wesley Terpstra 7*c40b6df8SAnup Patel * Paul Walmsley 8*c40b6df8SAnup Patel * 9*c40b6df8SAnup Patel * This program is free software; you can redistribute it and/or modify 10*c40b6df8SAnup Patel * it under the terms of the GNU General Public License version 2 as 11*c40b6df8SAnup Patel * published by the Free Software Foundation. 12*c40b6df8SAnup Patel * 13*c40b6df8SAnup Patel * This program is distributed in the hope that it will be useful, 14*c40b6df8SAnup Patel * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*c40b6df8SAnup Patel * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*c40b6df8SAnup Patel * GNU General Public License for more details. 17*c40b6df8SAnup Patel */ 18*c40b6df8SAnup Patel 19*c40b6df8SAnup Patel #ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H 20*c40b6df8SAnup Patel #define __LINUX_CLK_SIFIVE_FU540_PRCI_H 21*c40b6df8SAnup Patel 22*c40b6df8SAnup Patel /* Clock indexes for use by Device Tree data */ 23*c40b6df8SAnup Patel 24*c40b6df8SAnup Patel #define PRCI_CLK_COREPLL 0 25*c40b6df8SAnup Patel #define PRCI_CLK_DDRPLL 1 26*c40b6df8SAnup Patel #define PRCI_CLK_GEMGXLPLL 2 27*c40b6df8SAnup Patel #define PRCI_CLK_TLCLK 3 28*c40b6df8SAnup Patel 29*c40b6df8SAnup Patel #endif 30