1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Andes Technology Corporation 4 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 5 */ 6 7 #include <common.h> 8 9 void invalidate_icache_all(void) 10 { 11 asm volatile ("fence.i" ::: "memory"); 12 } 13 14 void flush_dcache_all(void) 15 { 16 asm volatile ("fence" :::"memory"); 17 } 18 void flush_dcache_range(unsigned long start, unsigned long end) 19 { 20 flush_dcache_all(); 21 } 22 23 void invalidate_icache_range(unsigned long start, unsigned long end) 24 { 25 /* 26 * RISC-V does not have an instruction for invalidating parts of the 27 * instruction cache. Invalidate all of it instead. 28 */ 29 invalidate_icache_all(); 30 } 31 32 void invalidate_dcache_range(unsigned long start, unsigned long end) 33 { 34 flush_dcache_all(); 35 } 36 37 void cache_flush(void) 38 { 39 invalidate_icache_all(); 40 flush_dcache_all(); 41 } 42 43 void flush_cache(unsigned long addr, unsigned long size) 44 { 45 invalidate_icache_all(); 46 flush_dcache_all(); 47 } 48 49 __weak void icache_enable(void) 50 { 51 } 52 53 __weak void icache_disable(void) 54 { 55 } 56 57 __weak int icache_status(void) 58 { 59 return 0; 60 } 61 62 __weak void dcache_enable(void) 63 { 64 } 65 66 __weak void dcache_disable(void) 67 { 68 } 69 70 __weak int dcache_status(void) 71 { 72 return 0; 73 } 74