1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2017 Microsemi Corporation. 4 * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> 5 */ 6 7 #ifndef RISCV_CSR_ENCODING_H 8 #define RISCV_CSR_ENCODING_H 9 10 #define MSTATUS_UIE 0x00000001 11 #define MSTATUS_SIE 0x00000002 12 #define MSTATUS_HIE 0x00000004 13 #define MSTATUS_MIE 0x00000008 14 #define MSTATUS_UPIE 0x00000010 15 #define MSTATUS_SPIE 0x00000020 16 #define MSTATUS_HPIE 0x00000040 17 #define MSTATUS_MPIE 0x00000080 18 #define MSTATUS_SPP 0x00000100 19 #define MSTATUS_HPP 0x00000600 20 #define MSTATUS_MPP 0x00001800 21 #define MSTATUS_FS 0x00006000 22 #define MSTATUS_XS 0x00018000 23 #define MSTATUS_MPRV 0x00020000 24 #define MSTATUS_PUM 0x00040000 25 #define MSTATUS_VM 0x1F000000 26 #define MSTATUS32_SD 0x80000000 27 #define MSTATUS64_SD 0x8000000000000000 28 29 #define MCAUSE32_CAUSE 0x7FFFFFFF 30 #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF 31 #define MCAUSE32_INT 0x80000000 32 #define MCAUSE64_INT 0x8000000000000000 33 34 #define SSTATUS_UIE 0x00000001 35 #define SSTATUS_SIE 0x00000002 36 #define SSTATUS_UPIE 0x00000010 37 #define SSTATUS_SPIE 0x00000020 38 #define SSTATUS_SPP 0x00000100 39 #define SSTATUS_FS 0x00006000 40 #define SSTATUS_XS 0x00018000 41 #define SSTATUS_PUM 0x00040000 42 #define SSTATUS32_SD 0x80000000 43 #define SSTATUS64_SD 0x8000000000000000 44 45 #define MIP_SSIP BIT(IRQ_S_SOFT) 46 #define MIP_HSIP BIT(IRQ_H_SOFT) 47 #define MIP_MSIP BIT(IRQ_M_SOFT) 48 #define MIP_STIP BIT(IRQ_S_TIMER) 49 #define MIP_HTIP BIT(IRQ_H_TIMER) 50 #define MIP_MTIP BIT(IRQ_M_TIMER) 51 #define MIP_SEIP BIT(IRQ_S_EXT) 52 #define MIP_HEIP BIT(IRQ_H_EXT) 53 #define MIP_MEIP BIT(IRQ_M_EXT) 54 55 #define SIP_SSIP MIP_SSIP 56 #define SIP_STIP MIP_STIP 57 58 #define PRV_U 0 59 #define PRV_S 1 60 #define PRV_H 2 61 #define PRV_M 3 62 63 #define VM_MBARE 0 64 #define VM_MBB 1 65 #define VM_MBBID 2 66 #define VM_SV32 8 67 #define VM_SV39 9 68 #define VM_SV48 10 69 70 #define IRQ_S_SOFT 1 71 #define IRQ_H_SOFT 2 72 #define IRQ_M_SOFT 3 73 #define IRQ_S_TIMER 5 74 #define IRQ_H_TIMER 6 75 #define IRQ_M_TIMER 7 76 #define IRQ_S_EXT 9 77 #define IRQ_H_EXT 10 78 #define IRQ_M_EXT 11 79 #define IRQ_COP 12 80 #define IRQ_HOST 13 81 82 #define DEFAULT_RSTVEC 0x00001000 83 #define DEFAULT_NMIVEC 0x00001004 84 #define DEFAULT_MTVEC 0x00001010 85 #define CONFIG_STRING_ADDR 0x0000100C 86 #define EXT_IO_BASE 0x40000000 87 #define DRAM_BASE 0x80000000 88 89 // page table entry (PTE) fields 90 #define PTE_V 0x001 // Valid 91 #define PTE_TYPE 0x01E // Type 92 #define PTE_R 0x020 // Referenced 93 #define PTE_D 0x040 // Dirty 94 #define PTE_SOFT 0x380 // Reserved for Software 95 96 #define PTE_TYPE_TABLE 0x00 97 #define PTE_TYPE_TABLE_GLOBAL 0x02 98 #define PTE_TYPE_URX_SR 0x04 99 #define PTE_TYPE_URWX_SRW 0x06 100 #define PTE_TYPE_UR_SR 0x08 101 #define PTE_TYPE_URW_SRW 0x0A 102 #define PTE_TYPE_URX_SRX 0x0C 103 #define PTE_TYPE_URWX_SRWX0x0E 104 #define PTE_TYPE_SR 0x10 105 #define PTE_TYPE_SRW 0x12 106 #define PTE_TYPE_SRX 0x14 107 #define PTE_TYPE_SRWX 0x16 108 #define PTE_TYPE_SR_GLOBAL 0x18 109 #define PTE_TYPE_SRW_GLOBAL 0x1A 110 #define PTE_TYPE_SRX_GLOBAL 0x1C 111 #define PTE_TYPE_SRWX_GLOBAL 0x1E 112 113 #define PTE_PPN_SHIFT 10 114 115 #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) 116 #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) 117 #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) 118 #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) 119 #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) 120 #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) 121 #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) 122 123 #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ 124 typeof(_PTE) (PTE) = (_PTE); \ 125 typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ 126 ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ 127 (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ 128 ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) 129 130 #ifdef __riscv 131 #ifdef CONFIG_64BIT 132 # define MSTATUS_SD MSTATUS64_SD 133 # define SSTATUS_SD SSTATUS64_SD 134 # define MCAUSE_INT MCAUSE64_INT 135 # define MCAUSE_CAUSE MCAUSE64_CAUSE 136 # define RISCV_PGLEVEL_BITS 9 137 #else 138 # define MSTATUS_SD MSTATUS32_SD 139 # define SSTATUS_SD SSTATUS32_SD 140 # define RISCV_PGLEVEL_BITS 10 141 # define MCAUSE_INT MCAUSE32_INT 142 # define MCAUSE_CAUSE MCAUSE32_CAUSE 143 #endif 144 #define RISCV_PGSHIFT 12 145 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) 146 147 #ifndef __ASSEMBLER__ 148 149 #ifdef __GNUC__ 150 151 #define read_csr(reg) ({ unsigned long __tmp; \ 152 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 153 __tmp; }) 154 155 #define write_csr(reg, _val) ({ \ 156 typeof(_val) (val) = (_val); \ 157 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 158 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 159 else \ 160 asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 161 162 #define swap_csr(reg, _val) ({ unsigned long __tmp; \ 163 typeof(_val) (val) = (_val); \ 164 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 165 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ 166 else \ 167 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ 168 __tmp; }) 169 170 #define set_csr(reg, _bit) ({ unsigned long __tmp; \ 171 typeof(_bit) (bit) = (_bit); \ 172 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 173 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 174 else \ 175 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 176 __tmp; }) 177 178 #define clear_csr(reg, _bit) ({ unsigned long __tmp; \ 179 typeof(_bit) (bit) = (_bit); \ 180 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 181 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 182 else \ 183 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 184 __tmp; }) 185 186 #define rdtime() read_csr(time) 187 #define rdcycle() read_csr(cycle) 188 #define rdinstret() read_csr(instret) 189 190 #endif 191 #endif 192 #endif 193 #endif 194