183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26020faf6SRick Chen /* 36020faf6SRick Chen * Copyright (c) 2017 Microsemi Corporation. 46020faf6SRick Chen * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> 56020faf6SRick Chen */ 66020faf6SRick Chen 76020faf6SRick Chen #ifndef RISCV_CSR_ENCODING_H 86020faf6SRick Chen #define RISCV_CSR_ENCODING_H 96020faf6SRick Chen 106020faf6SRick Chen #define MSTATUS_UIE 0x00000001 116020faf6SRick Chen #define MSTATUS_SIE 0x00000002 126020faf6SRick Chen #define MSTATUS_HIE 0x00000004 136020faf6SRick Chen #define MSTATUS_MIE 0x00000008 146020faf6SRick Chen #define MSTATUS_UPIE 0x00000010 156020faf6SRick Chen #define MSTATUS_SPIE 0x00000020 166020faf6SRick Chen #define MSTATUS_HPIE 0x00000040 176020faf6SRick Chen #define MSTATUS_MPIE 0x00000080 186020faf6SRick Chen #define MSTATUS_SPP 0x00000100 196020faf6SRick Chen #define MSTATUS_HPP 0x00000600 206020faf6SRick Chen #define MSTATUS_MPP 0x00001800 216020faf6SRick Chen #define MSTATUS_FS 0x00006000 226020faf6SRick Chen #define MSTATUS_XS 0x00018000 236020faf6SRick Chen #define MSTATUS_MPRV 0x00020000 246020faf6SRick Chen #define MSTATUS_PUM 0x00040000 256020faf6SRick Chen #define MSTATUS_VM 0x1F000000 266020faf6SRick Chen #define MSTATUS32_SD 0x80000000 276020faf6SRick Chen #define MSTATUS64_SD 0x8000000000000000 286020faf6SRick Chen 296020faf6SRick Chen #define MCAUSE32_CAUSE 0x7FFFFFFF 306020faf6SRick Chen #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF 316020faf6SRick Chen #define MCAUSE32_INT 0x80000000 326020faf6SRick Chen #define MCAUSE64_INT 0x8000000000000000 336020faf6SRick Chen 346020faf6SRick Chen #define SSTATUS_UIE 0x00000001 356020faf6SRick Chen #define SSTATUS_SIE 0x00000002 366020faf6SRick Chen #define SSTATUS_UPIE 0x00000010 376020faf6SRick Chen #define SSTATUS_SPIE 0x00000020 386020faf6SRick Chen #define SSTATUS_SPP 0x00000100 396020faf6SRick Chen #define SSTATUS_FS 0x00006000 406020faf6SRick Chen #define SSTATUS_XS 0x00018000 416020faf6SRick Chen #define SSTATUS_PUM 0x00040000 426020faf6SRick Chen #define SSTATUS32_SD 0x80000000 436020faf6SRick Chen #define SSTATUS64_SD 0x8000000000000000 446020faf6SRick Chen 456020faf6SRick Chen #define MIP_SSIP BIT(IRQ_S_SOFT) 466020faf6SRick Chen #define MIP_HSIP BIT(IRQ_H_SOFT) 476020faf6SRick Chen #define MIP_MSIP BIT(IRQ_M_SOFT) 486020faf6SRick Chen #define MIP_STIP BIT(IRQ_S_TIMER) 496020faf6SRick Chen #define MIP_HTIP BIT(IRQ_H_TIMER) 506020faf6SRick Chen #define MIP_MTIP BIT(IRQ_M_TIMER) 516020faf6SRick Chen #define MIP_SEIP BIT(IRQ_S_EXT) 526020faf6SRick Chen #define MIP_HEIP BIT(IRQ_H_EXT) 536020faf6SRick Chen #define MIP_MEIP BIT(IRQ_M_EXT) 546020faf6SRick Chen 556020faf6SRick Chen #define SIP_SSIP MIP_SSIP 566020faf6SRick Chen #define SIP_STIP MIP_STIP 576020faf6SRick Chen 586020faf6SRick Chen #define PRV_U 0 596020faf6SRick Chen #define PRV_S 1 606020faf6SRick Chen #define PRV_H 2 616020faf6SRick Chen #define PRV_M 3 626020faf6SRick Chen 636020faf6SRick Chen #define VM_MBARE 0 646020faf6SRick Chen #define VM_MBB 1 656020faf6SRick Chen #define VM_MBBID 2 666020faf6SRick Chen #define VM_SV32 8 676020faf6SRick Chen #define VM_SV39 9 686020faf6SRick Chen #define VM_SV48 10 696020faf6SRick Chen 706020faf6SRick Chen #define IRQ_S_SOFT 1 716020faf6SRick Chen #define IRQ_H_SOFT 2 726020faf6SRick Chen #define IRQ_M_SOFT 3 736020faf6SRick Chen #define IRQ_S_TIMER 5 746020faf6SRick Chen #define IRQ_H_TIMER 6 756020faf6SRick Chen #define IRQ_M_TIMER 7 766020faf6SRick Chen #define IRQ_S_EXT 9 776020faf6SRick Chen #define IRQ_H_EXT 10 786020faf6SRick Chen #define IRQ_M_EXT 11 796020faf6SRick Chen #define IRQ_COP 12 806020faf6SRick Chen #define IRQ_HOST 13 816020faf6SRick Chen 826020faf6SRick Chen #define DEFAULT_RSTVEC 0x00001000 836020faf6SRick Chen #define DEFAULT_NMIVEC 0x00001004 846020faf6SRick Chen #define DEFAULT_MTVEC 0x00001010 856020faf6SRick Chen #define CONFIG_STRING_ADDR 0x0000100C 866020faf6SRick Chen #define EXT_IO_BASE 0x40000000 876020faf6SRick Chen #define DRAM_BASE 0x80000000 886020faf6SRick Chen 896020faf6SRick Chen // page table entry (PTE) fields 906020faf6SRick Chen #define PTE_V 0x001 // Valid 916020faf6SRick Chen #define PTE_TYPE 0x01E // Type 926020faf6SRick Chen #define PTE_R 0x020 // Referenced 936020faf6SRick Chen #define PTE_D 0x040 // Dirty 946020faf6SRick Chen #define PTE_SOFT 0x380 // Reserved for Software 956020faf6SRick Chen 966020faf6SRick Chen #define PTE_TYPE_TABLE 0x00 976020faf6SRick Chen #define PTE_TYPE_TABLE_GLOBAL 0x02 986020faf6SRick Chen #define PTE_TYPE_URX_SR 0x04 996020faf6SRick Chen #define PTE_TYPE_URWX_SRW 0x06 1006020faf6SRick Chen #define PTE_TYPE_UR_SR 0x08 1016020faf6SRick Chen #define PTE_TYPE_URW_SRW 0x0A 1026020faf6SRick Chen #define PTE_TYPE_URX_SRX 0x0C 1036020faf6SRick Chen #define PTE_TYPE_URWX_SRWX0x0E 1046020faf6SRick Chen #define PTE_TYPE_SR 0x10 1056020faf6SRick Chen #define PTE_TYPE_SRW 0x12 1066020faf6SRick Chen #define PTE_TYPE_SRX 0x14 1076020faf6SRick Chen #define PTE_TYPE_SRWX 0x16 1086020faf6SRick Chen #define PTE_TYPE_SR_GLOBAL 0x18 1096020faf6SRick Chen #define PTE_TYPE_SRW_GLOBAL 0x1A 1106020faf6SRick Chen #define PTE_TYPE_SRX_GLOBAL 0x1C 1116020faf6SRick Chen #define PTE_TYPE_SRWX_GLOBAL 0x1E 1126020faf6SRick Chen 1136020faf6SRick Chen #define PTE_PPN_SHIFT 10 1146020faf6SRick Chen 1156020faf6SRick Chen #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) 1166020faf6SRick Chen #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) 1176020faf6SRick Chen #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) 1186020faf6SRick Chen #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) 1196020faf6SRick Chen #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) 1206020faf6SRick Chen #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) 1216020faf6SRick Chen #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) 1226020faf6SRick Chen 123bc0818a6SRick Chen #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ 124bc0818a6SRick Chen typeof(_PTE) (PTE) = (_PTE); \ 125bc0818a6SRick Chen typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ 1266020faf6SRick Chen ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ 1276020faf6SRick Chen (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ 1286020faf6SRick Chen ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) 1296020faf6SRick Chen 1306020faf6SRick Chen #ifdef __riscv 131*e5ea1e58SBin Meng 1326020faf6SRick Chen #ifdef CONFIG_64BIT 1336020faf6SRick Chen # define MSTATUS_SD MSTATUS64_SD 1346020faf6SRick Chen # define SSTATUS_SD SSTATUS64_SD 1356020faf6SRick Chen # define MCAUSE_INT MCAUSE64_INT 1366020faf6SRick Chen # define MCAUSE_CAUSE MCAUSE64_CAUSE 1376020faf6SRick Chen # define RISCV_PGLEVEL_BITS 9 1386020faf6SRick Chen #else 1396020faf6SRick Chen # define MSTATUS_SD MSTATUS32_SD 1406020faf6SRick Chen # define SSTATUS_SD SSTATUS32_SD 1416020faf6SRick Chen # define RISCV_PGLEVEL_BITS 10 1426020faf6SRick Chen # define MCAUSE_INT MCAUSE32_INT 1436020faf6SRick Chen # define MCAUSE_CAUSE MCAUSE32_CAUSE 1446020faf6SRick Chen #endif 145*e5ea1e58SBin Meng 1466020faf6SRick Chen #define RISCV_PGSHIFT 12 1476020faf6SRick Chen #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) 1486020faf6SRick Chen 149*e5ea1e58SBin Meng #endif /* __riscv */ 1506020faf6SRick Chen 151*e5ea1e58SBin Meng #endif /* RISCV_CSR_ENCODING_H */ 152