183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26020faf6SRick Chen /* 36020faf6SRick Chen * Copyright (c) 2017 Microsemi Corporation. 46020faf6SRick Chen * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> 56020faf6SRick Chen */ 66020faf6SRick Chen 76020faf6SRick Chen #ifndef RISCV_CSR_ENCODING_H 86020faf6SRick Chen #define RISCV_CSR_ENCODING_H 96020faf6SRick Chen 10*d2db2a8fSAnup Patel #ifdef CONFIG_RISCV_SMODE 11*d2db2a8fSAnup Patel #define MODE_PREFIX(__suffix) s##__suffix 12*d2db2a8fSAnup Patel #else 13*d2db2a8fSAnup Patel #define MODE_PREFIX(__suffix) m##__suffix 14*d2db2a8fSAnup Patel #endif 15*d2db2a8fSAnup Patel 166020faf6SRick Chen #define MSTATUS_UIE 0x00000001 176020faf6SRick Chen #define MSTATUS_SIE 0x00000002 186020faf6SRick Chen #define MSTATUS_HIE 0x00000004 196020faf6SRick Chen #define MSTATUS_MIE 0x00000008 206020faf6SRick Chen #define MSTATUS_UPIE 0x00000010 216020faf6SRick Chen #define MSTATUS_SPIE 0x00000020 226020faf6SRick Chen #define MSTATUS_HPIE 0x00000040 236020faf6SRick Chen #define MSTATUS_MPIE 0x00000080 246020faf6SRick Chen #define MSTATUS_SPP 0x00000100 256020faf6SRick Chen #define MSTATUS_HPP 0x00000600 266020faf6SRick Chen #define MSTATUS_MPP 0x00001800 276020faf6SRick Chen #define MSTATUS_FS 0x00006000 286020faf6SRick Chen #define MSTATUS_XS 0x00018000 296020faf6SRick Chen #define MSTATUS_MPRV 0x00020000 306020faf6SRick Chen #define MSTATUS_PUM 0x00040000 316020faf6SRick Chen #define MSTATUS_VM 0x1F000000 326020faf6SRick Chen #define MSTATUS32_SD 0x80000000 336020faf6SRick Chen #define MSTATUS64_SD 0x8000000000000000 346020faf6SRick Chen 356020faf6SRick Chen #define MCAUSE32_CAUSE 0x7FFFFFFF 366020faf6SRick Chen #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF 376020faf6SRick Chen #define MCAUSE32_INT 0x80000000 386020faf6SRick Chen #define MCAUSE64_INT 0x8000000000000000 396020faf6SRick Chen 406020faf6SRick Chen #define SSTATUS_UIE 0x00000001 416020faf6SRick Chen #define SSTATUS_SIE 0x00000002 426020faf6SRick Chen #define SSTATUS_UPIE 0x00000010 436020faf6SRick Chen #define SSTATUS_SPIE 0x00000020 446020faf6SRick Chen #define SSTATUS_SPP 0x00000100 456020faf6SRick Chen #define SSTATUS_FS 0x00006000 466020faf6SRick Chen #define SSTATUS_XS 0x00018000 476020faf6SRick Chen #define SSTATUS_PUM 0x00040000 486020faf6SRick Chen #define SSTATUS32_SD 0x80000000 496020faf6SRick Chen #define SSTATUS64_SD 0x8000000000000000 506020faf6SRick Chen 516020faf6SRick Chen #define MIP_SSIP BIT(IRQ_S_SOFT) 526020faf6SRick Chen #define MIP_HSIP BIT(IRQ_H_SOFT) 536020faf6SRick Chen #define MIP_MSIP BIT(IRQ_M_SOFT) 546020faf6SRick Chen #define MIP_STIP BIT(IRQ_S_TIMER) 556020faf6SRick Chen #define MIP_HTIP BIT(IRQ_H_TIMER) 566020faf6SRick Chen #define MIP_MTIP BIT(IRQ_M_TIMER) 576020faf6SRick Chen #define MIP_SEIP BIT(IRQ_S_EXT) 586020faf6SRick Chen #define MIP_HEIP BIT(IRQ_H_EXT) 596020faf6SRick Chen #define MIP_MEIP BIT(IRQ_M_EXT) 606020faf6SRick Chen 616020faf6SRick Chen #define SIP_SSIP MIP_SSIP 626020faf6SRick Chen #define SIP_STIP MIP_STIP 636020faf6SRick Chen 646020faf6SRick Chen #define PRV_U 0 656020faf6SRick Chen #define PRV_S 1 666020faf6SRick Chen #define PRV_H 2 676020faf6SRick Chen #define PRV_M 3 686020faf6SRick Chen 696020faf6SRick Chen #define VM_MBARE 0 706020faf6SRick Chen #define VM_MBB 1 716020faf6SRick Chen #define VM_MBBID 2 726020faf6SRick Chen #define VM_SV32 8 736020faf6SRick Chen #define VM_SV39 9 746020faf6SRick Chen #define VM_SV48 10 756020faf6SRick Chen 766020faf6SRick Chen #define IRQ_S_SOFT 1 776020faf6SRick Chen #define IRQ_H_SOFT 2 786020faf6SRick Chen #define IRQ_M_SOFT 3 796020faf6SRick Chen #define IRQ_S_TIMER 5 806020faf6SRick Chen #define IRQ_H_TIMER 6 816020faf6SRick Chen #define IRQ_M_TIMER 7 826020faf6SRick Chen #define IRQ_S_EXT 9 836020faf6SRick Chen #define IRQ_H_EXT 10 846020faf6SRick Chen #define IRQ_M_EXT 11 856020faf6SRick Chen #define IRQ_COP 12 866020faf6SRick Chen #define IRQ_HOST 13 876020faf6SRick Chen 886020faf6SRick Chen #define DEFAULT_RSTVEC 0x00001000 896020faf6SRick Chen #define DEFAULT_NMIVEC 0x00001004 906020faf6SRick Chen #define DEFAULT_MTVEC 0x00001010 916020faf6SRick Chen #define CONFIG_STRING_ADDR 0x0000100C 926020faf6SRick Chen #define EXT_IO_BASE 0x40000000 936020faf6SRick Chen #define DRAM_BASE 0x80000000 946020faf6SRick Chen 956020faf6SRick Chen // page table entry (PTE) fields 966020faf6SRick Chen #define PTE_V 0x001 // Valid 976020faf6SRick Chen #define PTE_TYPE 0x01E // Type 986020faf6SRick Chen #define PTE_R 0x020 // Referenced 996020faf6SRick Chen #define PTE_D 0x040 // Dirty 1006020faf6SRick Chen #define PTE_SOFT 0x380 // Reserved for Software 1016020faf6SRick Chen 1026020faf6SRick Chen #define PTE_TYPE_TABLE 0x00 1036020faf6SRick Chen #define PTE_TYPE_TABLE_GLOBAL 0x02 1046020faf6SRick Chen #define PTE_TYPE_URX_SR 0x04 1056020faf6SRick Chen #define PTE_TYPE_URWX_SRW 0x06 1066020faf6SRick Chen #define PTE_TYPE_UR_SR 0x08 1076020faf6SRick Chen #define PTE_TYPE_URW_SRW 0x0A 1086020faf6SRick Chen #define PTE_TYPE_URX_SRX 0x0C 1096020faf6SRick Chen #define PTE_TYPE_URWX_SRWX0x0E 1106020faf6SRick Chen #define PTE_TYPE_SR 0x10 1116020faf6SRick Chen #define PTE_TYPE_SRW 0x12 1126020faf6SRick Chen #define PTE_TYPE_SRX 0x14 1136020faf6SRick Chen #define PTE_TYPE_SRWX 0x16 1146020faf6SRick Chen #define PTE_TYPE_SR_GLOBAL 0x18 1156020faf6SRick Chen #define PTE_TYPE_SRW_GLOBAL 0x1A 1166020faf6SRick Chen #define PTE_TYPE_SRX_GLOBAL 0x1C 1176020faf6SRick Chen #define PTE_TYPE_SRWX_GLOBAL 0x1E 1186020faf6SRick Chen 1196020faf6SRick Chen #define PTE_PPN_SHIFT 10 1206020faf6SRick Chen 1216020faf6SRick Chen #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) 1226020faf6SRick Chen #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) 1236020faf6SRick Chen #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) 1246020faf6SRick Chen #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) 1256020faf6SRick Chen #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) 1266020faf6SRick Chen #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) 1276020faf6SRick Chen #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) 1286020faf6SRick Chen 129bc0818a6SRick Chen #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ 130bc0818a6SRick Chen typeof(_PTE) (PTE) = (_PTE); \ 131bc0818a6SRick Chen typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ 1326020faf6SRick Chen ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ 1336020faf6SRick Chen (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ 1346020faf6SRick Chen ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) 1356020faf6SRick Chen 1366020faf6SRick Chen #ifdef __riscv 137e5ea1e58SBin Meng 1386020faf6SRick Chen #ifdef CONFIG_64BIT 1396020faf6SRick Chen # define MSTATUS_SD MSTATUS64_SD 1406020faf6SRick Chen # define SSTATUS_SD SSTATUS64_SD 1416020faf6SRick Chen # define MCAUSE_INT MCAUSE64_INT 1426020faf6SRick Chen # define MCAUSE_CAUSE MCAUSE64_CAUSE 1436020faf6SRick Chen # define RISCV_PGLEVEL_BITS 9 1446020faf6SRick Chen #else 1456020faf6SRick Chen # define MSTATUS_SD MSTATUS32_SD 1466020faf6SRick Chen # define SSTATUS_SD SSTATUS32_SD 1476020faf6SRick Chen # define RISCV_PGLEVEL_BITS 10 1486020faf6SRick Chen # define MCAUSE_INT MCAUSE32_INT 1496020faf6SRick Chen # define MCAUSE_CAUSE MCAUSE32_CAUSE 1506020faf6SRick Chen #endif 151e5ea1e58SBin Meng 1526020faf6SRick Chen #define RISCV_PGSHIFT 12 1536020faf6SRick Chen #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) 1546020faf6SRick Chen 155e5ea1e58SBin Meng #endif /* __riscv */ 1566020faf6SRick Chen 157e5ea1e58SBin Meng #endif /* RISCV_CSR_ENCODING_H */ 158