1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 * 5 * Taken from Linux arch/riscv/include/asm/csr.h 6 */ 7 8 #ifndef _ASM_RISCV_CSR_H 9 #define _ASM_RISCV_CSR_H 10 11 /* Status register flags */ 12 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 13 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 14 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 15 #define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */ 16 17 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 18 #define SR_FS_OFF _AC(0x00000000, UL) 19 #define SR_FS_INITIAL _AC(0x00002000, UL) 20 #define SR_FS_CLEAN _AC(0x00004000, UL) 21 #define SR_FS_DIRTY _AC(0x00006000, UL) 22 23 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 24 #define SR_XS_OFF _AC(0x00000000, UL) 25 #define SR_XS_INITIAL _AC(0x00008000, UL) 26 #define SR_XS_CLEAN _AC(0x00010000, UL) 27 #define SR_XS_DIRTY _AC(0x00018000, UL) 28 29 #ifndef CONFIG_64BIT 30 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 31 #else 32 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 33 #endif 34 35 /* SATP flags */ 36 #if __riscv_xlen == 32 37 #define SATP_PPN _AC(0x003FFFFF, UL) 38 #define SATP_MODE_32 _AC(0x80000000, UL) 39 #define SATP_MODE SATP_MODE_32 40 #else 41 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 42 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 43 #define SATP_MODE SATP_MODE_39 44 #endif 45 46 /* Interrupt Enable and Interrupt Pending flags */ 47 #define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ 48 #define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ 49 50 #define EXC_INST_MISALIGNED 0 51 #define EXC_INST_ACCESS 1 52 #define EXC_BREAKPOINT 3 53 #define EXC_LOAD_ACCESS 5 54 #define EXC_STORE_ACCESS 7 55 #define EXC_SYSCALL 8 56 #define EXC_INST_PAGE_FAULT 12 57 #define EXC_LOAD_PAGE_FAULT 13 58 #define EXC_STORE_PAGE_FAULT 15 59 60 #ifndef __ASSEMBLY__ 61 62 #define csr_swap(csr, val) \ 63 ({ \ 64 unsigned long __v = (unsigned long)(val); \ 65 __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ 66 : "=r" (__v) : "rK" (__v) \ 67 : "memory"); \ 68 __v; \ 69 }) 70 71 #define csr_read(csr) \ 72 ({ \ 73 register unsigned long __v; \ 74 __asm__ __volatile__ ("csrr %0, " #csr \ 75 : "=r" (__v) : \ 76 : "memory"); \ 77 __v; \ 78 }) 79 80 #define csr_write(csr, val) \ 81 ({ \ 82 unsigned long __v = (unsigned long)(val); \ 83 __asm__ __volatile__ ("csrw " #csr ", %0" \ 84 : : "rK" (__v) \ 85 : "memory"); \ 86 }) 87 88 #define csr_read_set(csr, val) \ 89 ({ \ 90 unsigned long __v = (unsigned long)(val); \ 91 __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ 92 : "=r" (__v) : "rK" (__v) \ 93 : "memory"); \ 94 __v; \ 95 }) 96 97 #define csr_set(csr, val) \ 98 ({ \ 99 unsigned long __v = (unsigned long)(val); \ 100 __asm__ __volatile__ ("csrs " #csr ", %0" \ 101 : : "rK" (__v) \ 102 : "memory"); \ 103 }) 104 105 #define csr_read_clear(csr, val) \ 106 ({ \ 107 unsigned long __v = (unsigned long)(val); \ 108 __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ 109 : "=r" (__v) : "rK" (__v) \ 110 : "memory"); \ 111 __v; \ 112 }) 113 114 #define csr_clear(csr, val) \ 115 ({ \ 116 unsigned long __v = (unsigned long)(val); \ 117 __asm__ __volatile__ ("csrc " #csr ", %0" \ 118 : : "rK" (__v) \ 119 : "memory"); \ 120 }) 121 122 #endif /* __ASSEMBLY__ */ 123 124 #endif /* _ASM_RISCV_CSR_H */ 125