12fab2e9cSBin Meng /* SPDX-License-Identifier: GPL-2.0 */ 22fab2e9cSBin Meng /* 32fab2e9cSBin Meng * Copyright (C) 2015 Regents of the University of California 42fab2e9cSBin Meng * 52fab2e9cSBin Meng * Taken from Linux arch/riscv/include/asm/csr.h 62fab2e9cSBin Meng */ 72fab2e9cSBin Meng 82fab2e9cSBin Meng #ifndef _ASM_RISCV_CSR_H 92fab2e9cSBin Meng #define _ASM_RISCV_CSR_H 102fab2e9cSBin Meng 115c8fd32bSBaruch Siach #include <linux/const.h> 125c8fd32bSBaruch Siach 132fab2e9cSBin Meng /* Status register flags */ 142fab2e9cSBin Meng #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 152fab2e9cSBin Meng #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 162fab2e9cSBin Meng #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 172fab2e9cSBin Meng #define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */ 182fab2e9cSBin Meng 192fab2e9cSBin Meng #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 202fab2e9cSBin Meng #define SR_FS_OFF _AC(0x00000000, UL) 212fab2e9cSBin Meng #define SR_FS_INITIAL _AC(0x00002000, UL) 222fab2e9cSBin Meng #define SR_FS_CLEAN _AC(0x00004000, UL) 232fab2e9cSBin Meng #define SR_FS_DIRTY _AC(0x00006000, UL) 242fab2e9cSBin Meng 252fab2e9cSBin Meng #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 262fab2e9cSBin Meng #define SR_XS_OFF _AC(0x00000000, UL) 272fab2e9cSBin Meng #define SR_XS_INITIAL _AC(0x00008000, UL) 282fab2e9cSBin Meng #define SR_XS_CLEAN _AC(0x00010000, UL) 292fab2e9cSBin Meng #define SR_XS_DIRTY _AC(0x00018000, UL) 302fab2e9cSBin Meng 312fab2e9cSBin Meng #ifndef CONFIG_64BIT 322fab2e9cSBin Meng #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 332fab2e9cSBin Meng #else 342fab2e9cSBin Meng #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 352fab2e9cSBin Meng #endif 362fab2e9cSBin Meng 372fab2e9cSBin Meng /* SATP flags */ 382fab2e9cSBin Meng #if __riscv_xlen == 32 392fab2e9cSBin Meng #define SATP_PPN _AC(0x003FFFFF, UL) 402fab2e9cSBin Meng #define SATP_MODE_32 _AC(0x80000000, UL) 412fab2e9cSBin Meng #define SATP_MODE SATP_MODE_32 422fab2e9cSBin Meng #else 432fab2e9cSBin Meng #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 442fab2e9cSBin Meng #define SATP_MODE_39 _AC(0x8000000000000000, UL) 452fab2e9cSBin Meng #define SATP_MODE SATP_MODE_39 462fab2e9cSBin Meng #endif 472fab2e9cSBin Meng 482fab2e9cSBin Meng /* Interrupt Enable and Interrupt Pending flags */ 492fab2e9cSBin Meng #define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ 502fab2e9cSBin Meng #define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ 512fab2e9cSBin Meng 522fab2e9cSBin Meng #define EXC_INST_MISALIGNED 0 532fab2e9cSBin Meng #define EXC_INST_ACCESS 1 542fab2e9cSBin Meng #define EXC_BREAKPOINT 3 552fab2e9cSBin Meng #define EXC_LOAD_ACCESS 5 562fab2e9cSBin Meng #define EXC_STORE_ACCESS 7 572fab2e9cSBin Meng #define EXC_SYSCALL 8 582fab2e9cSBin Meng #define EXC_INST_PAGE_FAULT 12 592fab2e9cSBin Meng #define EXC_LOAD_PAGE_FAULT 13 602fab2e9cSBin Meng #define EXC_STORE_PAGE_FAULT 15 612fab2e9cSBin Meng 622fab2e9cSBin Meng #ifndef __ASSEMBLY__ 632fab2e9cSBin Meng 64*57fe5c64SBin Meng #define xcsr(csr) #csr 65*57fe5c64SBin Meng 662fab2e9cSBin Meng #define csr_swap(csr, val) \ 672fab2e9cSBin Meng ({ \ 682fab2e9cSBin Meng unsigned long __v = (unsigned long)(val); \ 69*57fe5c64SBin Meng __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \ 702fab2e9cSBin Meng : "=r" (__v) : "rK" (__v) \ 712fab2e9cSBin Meng : "memory"); \ 722fab2e9cSBin Meng __v; \ 732fab2e9cSBin Meng }) 742fab2e9cSBin Meng 752fab2e9cSBin Meng #define csr_read(csr) \ 762fab2e9cSBin Meng ({ \ 772fab2e9cSBin Meng register unsigned long __v; \ 78*57fe5c64SBin Meng __asm__ __volatile__ ("csrr %0, " xcsr(csr) \ 792fab2e9cSBin Meng : "=r" (__v) : \ 802fab2e9cSBin Meng : "memory"); \ 812fab2e9cSBin Meng __v; \ 822fab2e9cSBin Meng }) 832fab2e9cSBin Meng 842fab2e9cSBin Meng #define csr_write(csr, val) \ 852fab2e9cSBin Meng ({ \ 862fab2e9cSBin Meng unsigned long __v = (unsigned long)(val); \ 87*57fe5c64SBin Meng __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \ 882fab2e9cSBin Meng : : "rK" (__v) \ 892fab2e9cSBin Meng : "memory"); \ 902fab2e9cSBin Meng }) 912fab2e9cSBin Meng 922fab2e9cSBin Meng #define csr_read_set(csr, val) \ 932fab2e9cSBin Meng ({ \ 942fab2e9cSBin Meng unsigned long __v = (unsigned long)(val); \ 95*57fe5c64SBin Meng __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \ 962fab2e9cSBin Meng : "=r" (__v) : "rK" (__v) \ 972fab2e9cSBin Meng : "memory"); \ 982fab2e9cSBin Meng __v; \ 992fab2e9cSBin Meng }) 1002fab2e9cSBin Meng 1012fab2e9cSBin Meng #define csr_set(csr, val) \ 1022fab2e9cSBin Meng ({ \ 1032fab2e9cSBin Meng unsigned long __v = (unsigned long)(val); \ 104*57fe5c64SBin Meng __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \ 1052fab2e9cSBin Meng : : "rK" (__v) \ 1062fab2e9cSBin Meng : "memory"); \ 1072fab2e9cSBin Meng }) 1082fab2e9cSBin Meng 1092fab2e9cSBin Meng #define csr_read_clear(csr, val) \ 1102fab2e9cSBin Meng ({ \ 1112fab2e9cSBin Meng unsigned long __v = (unsigned long)(val); \ 112*57fe5c64SBin Meng __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \ 1132fab2e9cSBin Meng : "=r" (__v) : "rK" (__v) \ 1142fab2e9cSBin Meng : "memory"); \ 1152fab2e9cSBin Meng __v; \ 1162fab2e9cSBin Meng }) 1172fab2e9cSBin Meng 1182fab2e9cSBin Meng #define csr_clear(csr, val) \ 1192fab2e9cSBin Meng ({ \ 1202fab2e9cSBin Meng unsigned long __v = (unsigned long)(val); \ 121*57fe5c64SBin Meng __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \ 1222fab2e9cSBin Meng : : "rK" (__v) \ 1232fab2e9cSBin Meng : "memory"); \ 1242fab2e9cSBin Meng }) 1252fab2e9cSBin Meng 1262fab2e9cSBin Meng #endif /* __ASSEMBLY__ */ 1272fab2e9cSBin Meng 1282fab2e9cSBin Meng #endif /* _ASM_RISCV_CSR_H */ 129