1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017 Andes Technology Corporation 4 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 5 */ 6 7 #ifndef _ASM_RISCV_CACHE_H 8 #define _ASM_RISCV_CACHE_H 9 10 /* 11 * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. 12 * We use that value for aligning DMA buffers unless the board config has 13 * specified an alternate cache line size. 14 */ 15 #ifdef CONFIG_SYS_CACHELINE_SIZE 16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 17 #else 18 #define ARCH_DMA_MINALIGN 32 19 #endif 20 21 #endif /* _ASM_RISCV_CACHE_H */ 22