1/dts-v1/; 2 3/ { 4 #address-cells = <1>; 5 #size-cells = <1>; 6 compatible = "andestech,a25"; 7 model = "andestech,a25"; 8 9 aliases { 10 uart0 = &serial0; 11 spi0 = &spi; 12 }; 13 14 chosen { 15 bootargs = "console=ttyS0,38400n8 debug loglevel=7"; 16 stdout-path = "uart0:38400n8"; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 timebase-frequency = <60000000>; 23 CPU0: cpu@0 { 24 device_type = "cpu"; 25 reg = <0>; 26 status = "okay"; 27 compatible = "riscv"; 28 riscv,isa = "rv32imafdc"; 29 mmu-type = "riscv,sv32"; 30 clock-frequency = <60000000>; 31 d-cache-size = <0x8000>; 32 d-cache-line-size = <32>; 33 CPU0_intc: interrupt-controller { 34 #interrupt-cells = <1>; 35 interrupt-controller; 36 compatible = "riscv,cpu-intc"; 37 }; 38 }; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x00000000 0x40000000>; 44 }; 45 46 soc { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 compatible = "andestech,riscv-ae350-soc"; 50 ranges; 51 52 plic0: interrupt-controller@e4000000 { 53 compatible = "riscv,plic0"; 54 #address-cells = <1>; 55 #interrupt-cells = <1>; 56 interrupt-controller; 57 reg = <0xe4000000 0x2000000>; 58 riscv,ndev=<71>; 59 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; 60 }; 61 62 plic1: interrupt-controller@e6400000 { 63 compatible = "riscv,plic1"; 64 #address-cells = <1>; 65 #interrupt-cells = <1>; 66 interrupt-controller; 67 reg = <0xe6400000 0x400000>; 68 riscv,ndev=<1>; 69 interrupts-extended = <&CPU0_intc 3>; 70 }; 71 72 plmt0@e6000000 { 73 compatible = "riscv,plmt0"; 74 interrupts-extended = <&CPU0_intc 7>; 75 reg = <0xe6000000 0x100000>; 76 }; 77 }; 78 79 spiclk: virt_100mhz { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <100000000>; 83 }; 84 85 timer0: timer@f0400000 { 86 compatible = "andestech,atcpit100"; 87 reg = <0xf0400000 0x1000>; 88 clock-frequency = <60000000>; 89 interrupts = <3 4>; 90 interrupt-parent = <&plic0>; 91 }; 92 93 serial0: serial@f0300000 { 94 compatible = "andestech,uart16550", "ns16550a"; 95 reg = <0xf0300000 0x1000>; 96 interrupts = <9 4>; 97 clock-frequency = <19660800>; 98 reg-shift = <2>; 99 reg-offset = <32>; 100 no-loopback-test = <1>; 101 interrupt-parent = <&plic0>; 102 }; 103 104 mac0: mac@e0100000 { 105 compatible = "andestech,atmac100"; 106 reg = <0xe0100000 0x1000>; 107 interrupts = <19 4>; 108 interrupt-parent = <&plic0>; 109 }; 110 111 mmc0: mmc@f0e00000 { 112 compatible = "andestech,atfsdc010"; 113 max-frequency = <100000000>; 114 clock-freq-min-max = <400000 100000000>; 115 fifo-depth = <0x10>; 116 reg = <0xf0e00000 0x1000>; 117 interrupts = <18 4>; 118 cap-sd-highspeed; 119 interrupt-parent = <&plic0>; 120 }; 121 122 dma0: dma@f0c00000 { 123 compatible = "andestech,atcdmac300"; 124 reg = <0xf0c00000 0x1000>; 125 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; 126 dma-channels = <8>; 127 interrupt-parent = <&plic0>; 128 }; 129 130 lcd0: lcd@e0200000 { 131 compatible = "andestech,atflcdc100"; 132 reg = <0xe0200000 0x1000>; 133 interrupts = <20 4>; 134 interrupt-parent = <&plic0>; 135 }; 136 137 smc0: smc@e0400000 { 138 compatible = "andestech,atfsmc020"; 139 reg = <0xe0400000 0x1000>; 140 }; 141 142 snd0: snd@f0d00000 { 143 compatible = "andestech,atfac97"; 144 reg = <0xf0d00000 0x1000>; 145 interrupts = <17 4>; 146 interrupt-parent = <&plic0>; 147 }; 148 149 virtio_mmio@fe007000 { 150 interrupts = <0x17 0x4>; 151 interrupt-parent = <0x2>; 152 reg = <0xfe007000 0x1000>; 153 compatible = "virtio,mmio"; 154 }; 155 156 virtio_mmio@fe006000 { 157 interrupts = <0x16 0x4>; 158 interrupt-parent = <0x2>; 159 reg = <0xfe006000 0x1000>; 160 compatible = "virtio,mmio"; 161 }; 162 163 virtio_mmio@fe005000 { 164 interrupts = <0x15 0x4>; 165 interrupt-parent = <0x2>; 166 reg = <0xfe005000 0x1000>; 167 compatible = "virtio,mmio"; 168 }; 169 170 virtio_mmio@fe004000 { 171 interrupts = <0x14 0x4>; 172 interrupt-parent = <0x2>; 173 reg = <0xfe004000 0x1000>; 174 compatible = "virtio,mmio"; 175 }; 176 177 virtio_mmio@fe003000 { 178 interrupts = <0x13 0x4>; 179 interrupt-parent = <0x2>; 180 reg = <0xfe003000 0x1000>; 181 compatible = "virtio,mmio"; 182 }; 183 184 virtio_mmio@fe002000 { 185 interrupts = <0x12 0x4>; 186 interrupt-parent = <0x2>; 187 reg = <0xfe002000 0x1000>; 188 compatible = "virtio,mmio"; 189 }; 190 191 virtio_mmio@fe001000 { 192 interrupts = <0x11 0x4>; 193 interrupt-parent = <0x2>; 194 reg = <0xfe001000 0x1000>; 195 compatible = "virtio,mmio"; 196 }; 197 198 virtio_mmio@fe000000 { 199 interrupts = <0x10 0x4>; 200 interrupt-parent = <0x2>; 201 reg = <0xfe000000 0x1000>; 202 compatible = "virtio,mmio"; 203 }; 204 205 nor@0,0 { 206 compatible = "cfi-flash"; 207 reg = <0x88000000 0x1000>; 208 bank-width = <2>; 209 device-width = <1>; 210 }; 211 212 spi: spi@f0b00000 { 213 compatible = "andestech,atcspi200"; 214 reg = <0xf0b00000 0x1000>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 num-cs = <1>; 218 clocks = <&spiclk>; 219 interrupts = <4 4>; 220 interrupt-parent = <&plic0>; 221 flash@0 { 222 compatible = "spi-flash"; 223 spi-max-frequency = <50000000>; 224 reg = <0>; 225 spi-cpol; 226 spi-cpha; 227 }; 228 }; 229}; 230