1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * M-mode Trap Handler Code for RISC-V Core 4 * 5 * Copyright (c) 2017 Microsemi Corporation. 6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com> 7 * 8 * Copyright (C) 2017 Andes Technology Corporation 9 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 10 * 11 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> 12 */ 13 14#include <common.h> 15#include <asm/encoding.h> 16 17#ifdef CONFIG_32BIT 18#define LREG lw 19#define SREG sw 20#define REGBYTES 4 21#else 22#define LREG ld 23#define SREG sd 24#define REGBYTES 8 25#endif 26 27 .text 28 29 /* trap entry */ 30 .align 2 31 .global trap_entry 32trap_entry: 33 addi sp, sp, -32 * REGBYTES 34 SREG x1, 1 * REGBYTES(sp) 35 SREG x2, 2 * REGBYTES(sp) 36 SREG x3, 3 * REGBYTES(sp) 37 SREG x4, 4 * REGBYTES(sp) 38 SREG x5, 5 * REGBYTES(sp) 39 SREG x6, 6 * REGBYTES(sp) 40 SREG x7, 7 * REGBYTES(sp) 41 SREG x8, 8 * REGBYTES(sp) 42 SREG x9, 9 * REGBYTES(sp) 43 SREG x10, 10 * REGBYTES(sp) 44 SREG x11, 11 * REGBYTES(sp) 45 SREG x12, 12 * REGBYTES(sp) 46 SREG x13, 13 * REGBYTES(sp) 47 SREG x14, 14 * REGBYTES(sp) 48 SREG x15, 15 * REGBYTES(sp) 49 SREG x16, 16 * REGBYTES(sp) 50 SREG x17, 17 * REGBYTES(sp) 51 SREG x18, 18 * REGBYTES(sp) 52 SREG x19, 19 * REGBYTES(sp) 53 SREG x20, 20 * REGBYTES(sp) 54 SREG x21, 21 * REGBYTES(sp) 55 SREG x22, 22 * REGBYTES(sp) 56 SREG x23, 23 * REGBYTES(sp) 57 SREG x24, 24 * REGBYTES(sp) 58 SREG x25, 25 * REGBYTES(sp) 59 SREG x26, 26 * REGBYTES(sp) 60 SREG x27, 27 * REGBYTES(sp) 61 SREG x28, 28 * REGBYTES(sp) 62 SREG x29, 29 * REGBYTES(sp) 63 SREG x30, 30 * REGBYTES(sp) 64 SREG x31, 31 * REGBYTES(sp) 65 csrr a0, MODE_PREFIX(cause) 66 csrr a1, MODE_PREFIX(epc) 67 mv a2, sp 68 jal handle_trap 69 csrw MODE_PREFIX(epc), a0 70 71 LREG x1, 1 * REGBYTES(sp) 72 LREG x3, 3 * REGBYTES(sp) 73 LREG x4, 4 * REGBYTES(sp) 74 LREG x5, 5 * REGBYTES(sp) 75 LREG x6, 6 * REGBYTES(sp) 76 LREG x7, 7 * REGBYTES(sp) 77 LREG x8, 8 * REGBYTES(sp) 78 LREG x9, 9 * REGBYTES(sp) 79 LREG x10, 10 * REGBYTES(sp) 80 LREG x11, 11 * REGBYTES(sp) 81 LREG x12, 12 * REGBYTES(sp) 82 LREG x13, 13 * REGBYTES(sp) 83 LREG x14, 14 * REGBYTES(sp) 84 LREG x15, 15 * REGBYTES(sp) 85 LREG x16, 16 * REGBYTES(sp) 86 LREG x17, 17 * REGBYTES(sp) 87 LREG x18, 18 * REGBYTES(sp) 88 LREG x19, 19 * REGBYTES(sp) 89 LREG x20, 20 * REGBYTES(sp) 90 LREG x21, 21 * REGBYTES(sp) 91 LREG x22, 22 * REGBYTES(sp) 92 LREG x23, 23 * REGBYTES(sp) 93 LREG x24, 24 * REGBYTES(sp) 94 LREG x25, 25 * REGBYTES(sp) 95 LREG x26, 26 * REGBYTES(sp) 96 LREG x27, 27 * REGBYTES(sp) 97 LREG x28, 28 * REGBYTES(sp) 98 LREG x29, 29 * REGBYTES(sp) 99 LREG x30, 30 * REGBYTES(sp) 100 LREG x31, 31 * REGBYTES(sp) 101 LREG x2, 2 * REGBYTES(sp) 102 addi sp, sp, 32 * REGBYTES 103 MODE_PREFIX(ret) 104