1fdff1f96SAnup Patel // SPDX-License-Identifier: GPL-2.0+ 2fdff1f96SAnup Patel /* 3fdff1f96SAnup Patel * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> 4fdff1f96SAnup Patel */ 5fdff1f96SAnup Patel 6fdff1f96SAnup Patel #include <common.h> 7fdff1f96SAnup Patel #include <fdtdec.h> 8*26f4fd1cSAnup Patel #include <linux/sizes.h> 9*26f4fd1cSAnup Patel 10*26f4fd1cSAnup Patel DECLARE_GLOBAL_DATA_PTR; 11fdff1f96SAnup Patel dram_init(void)12fdff1f96SAnup Patelint dram_init(void) 13fdff1f96SAnup Patel { 14fdff1f96SAnup Patel return fdtdec_setup_mem_size_base(); 15fdff1f96SAnup Patel } 16fdff1f96SAnup Patel dram_init_banksize(void)17fdff1f96SAnup Patelint dram_init_banksize(void) 18fdff1f96SAnup Patel { 19fdff1f96SAnup Patel return fdtdec_setup_memory_banksize(); 20fdff1f96SAnup Patel } 21*26f4fd1cSAnup Patel board_get_usable_ram_top(ulong total_size)22*26f4fd1cSAnup Patelulong board_get_usable_ram_top(ulong total_size) 23*26f4fd1cSAnup Patel { 24*26f4fd1cSAnup Patel #ifdef CONFIG_64BIT 25*26f4fd1cSAnup Patel /* 26*26f4fd1cSAnup Patel * Ensure that we run from first 4GB so that all 27*26f4fd1cSAnup Patel * addresses used by U-Boot are 32bit addresses. 28*26f4fd1cSAnup Patel * 29*26f4fd1cSAnup Patel * This in-turn ensures that 32bit DMA capable 30*26f4fd1cSAnup Patel * devices work fine because DMA mapping APIs will 31*26f4fd1cSAnup Patel * provide 32bit DMA addresses only. 32*26f4fd1cSAnup Patel */ 33*26f4fd1cSAnup Patel if (gd->ram_top > SZ_4G) 34*26f4fd1cSAnup Patel return SZ_4G; 35*26f4fd1cSAnup Patel #endif 36*26f4fd1cSAnup Patel return gd->ram_top; 37*26f4fd1cSAnup Patel } 38