xref: /openbmc/u-boot/arch/riscv/cpu/cpu.c (revision 2d59ec84829ff339041667c857afe94d5160f4b4)
1  // SPDX-License-Identifier: GPL-2.0+
2  /*
3   * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4   */
5  
6  #include <common.h>
7  #include <cpu.h>
8  #include <dm.h>
9  #include <log.h>
10  #include <asm/csr.h>
11  #include <asm/encoding.h>
12  #include <dm/uclass-internal.h>
13  
14  /*
15   * prior_stage_fdt_address must be stored in the data section since it is used
16   * before the bss section is available.
17   */
18  phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
19  
20  static inline bool supports_extension(char ext)
21  {
22  #ifdef CONFIG_CPU
23  	struct udevice *dev;
24  	char desc[32];
25  
26  	uclass_find_first_device(UCLASS_CPU, &dev);
27  	if (!dev) {
28  		debug("unable to find the RISC-V cpu device\n");
29  		return false;
30  	}
31  	if (!cpu_get_desc(dev, desc, sizeof(desc))) {
32  		/* skip the first 4 characters (rv32|rv64) */
33  		if (strchr(desc + 4, ext))
34  			return true;
35  	}
36  
37  	return false;
38  #else  /* !CONFIG_CPU */
39  #ifdef CONFIG_RISCV_MMODE
40  	return csr_read(misa) & (1 << (ext - 'a'));
41  #else  /* !CONFIG_RISCV_MMODE */
42  #warning "There is no way to determine the available extensions in S-mode."
43  #warning "Please convert your board to use the RISC-V CPU driver."
44  	return false;
45  #endif /* CONFIG_RISCV_MMODE */
46  #endif /* CONFIG_CPU */
47  }
48  
49  static int riscv_cpu_probe(void)
50  {
51  #ifdef CONFIG_CPU
52  	int ret;
53  
54  	/* probe cpus so that RISC-V timer can be bound */
55  	ret = cpu_probe_all();
56  	if (ret)
57  		return log_msg_ret("RISC-V cpus probe failed\n", ret);
58  #endif
59  
60  	return 0;
61  }
62  
63  int arch_cpu_init_dm(void)
64  {
65  	int ret;
66  
67  	ret = riscv_cpu_probe();
68  	if (ret)
69  		return ret;
70  
71  	/* Enable FPU */
72  	if (supports_extension('d') || supports_extension('f')) {
73  		csr_set(MODE_PREFIX(status), MSTATUS_FS);
74  		csr_write(fcsr, 0);
75  	}
76  
77  	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
78  		/*
79  		 * Enable perf counters for cycle, time,
80  		 * and instret counters only
81  		 */
82  		csr_write(mcounteren, GENMASK(2, 0));
83  
84  		/* Disable paging */
85  		if (supports_extension('s'))
86  			csr_write(satp, 0);
87  	}
88  
89  	return 0;
90  }
91  
92  int arch_early_init_r(void)
93  {
94  	return riscv_cpu_probe();
95  }
96