1menu "RISC-V architecture" 2 depends on RISCV 3 4config SYS_ARCH 5 default "riscv" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_AX25_AE350 12 bool "Support ax25-ae350" 13 14config TARGET_QEMU_VIRT 15 bool "Support QEMU Virt Board" 16 17config TARGET_SIFIVE_FU540 18 bool "Support SiFive FU540 Board" 19 20endchoice 21 22# board-specific options below 23source "board/AndesTech/ax25-ae350/Kconfig" 24source "board/emulation/qemu-riscv/Kconfig" 25source "board/sifive/fu540/Kconfig" 26 27# platform-specific options below 28source "arch/riscv/cpu/ax25/Kconfig" 29source "arch/riscv/cpu/generic/Kconfig" 30 31# architecture-specific options below 32 33choice 34 prompt "Base ISA" 35 default ARCH_RV32I 36 37config ARCH_RV32I 38 bool "RV32I" 39 select 32BIT 40 help 41 Choose this option to target the RV32I base integer instruction set. 42 43config ARCH_RV64I 44 bool "RV64I" 45 select 64BIT 46 select PHYS_64BIT 47 help 48 Choose this option to target the RV64I base integer instruction set. 49 50endchoice 51 52choice 53 prompt "Code Model" 54 default CMODEL_MEDLOW 55 56config CMODEL_MEDLOW 57 bool "medium low code model" 58 help 59 U-Boot and its statically defined symbols must lie within a single 2 GiB 60 address range and must lie between absolute addresses -2 GiB and +2 GiB. 61 62config CMODEL_MEDANY 63 bool "medium any code model" 64 help 65 U-Boot and its statically defined symbols must be within any single 2 GiB 66 address range. 67 68endchoice 69 70choice 71 prompt "Run Mode" 72 default RISCV_MMODE 73 74config RISCV_MMODE 75 bool "Machine" 76 help 77 Choose this option to build U-Boot for RISC-V M-Mode. 78 79config RISCV_SMODE 80 bool "Supervisor" 81 help 82 Choose this option to build U-Boot for RISC-V S-Mode. 83 84endchoice 85 86config RISCV_ISA_C 87 bool "Emit compressed instructions" 88 default y 89 help 90 Adds "C" to the ISA subsets that the toolchain is allowed to emit 91 when building U-Boot, which results in compressed instructions in the 92 U-Boot binary. 93 94config RISCV_ISA_A 95 def_bool y 96 97config 32BIT 98 bool 99 100config 64BIT 101 bool 102 103config SIFIVE_CLINT 104 bool 105 depends on RISCV_MMODE 106 select REGMAP 107 select SYSCON 108 help 109 The SiFive CLINT block holds memory-mapped control and status registers 110 associated with software and timer interrupts. 111 112config RISCV_RDTIME 113 bool 114 default y if RISCV_SMODE 115 help 116 The provides the riscv_get_time() API that is implemented using the 117 standard rdtime instruction. This is the case for S-mode U-Boot, and 118 is useful for processors that support rdtime in M-mode too. 119 120config SYS_MALLOC_F_LEN 121 default 0x1000 122 123endmenu 124