1menu "RISC-V architecture" 2 depends on RISCV 3 4config SYS_ARCH 5 default "riscv" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_AX25_AE350 12 bool "Support ax25-ae350" 13 14config TARGET_QEMU_VIRT 15 bool "Support QEMU Virt Board" 16 17endchoice 18 19# board-specific options below 20source "board/AndesTech/ax25-ae350/Kconfig" 21source "board/emulation/qemu-riscv/Kconfig" 22 23# platform-specific options below 24source "arch/riscv/cpu/ax25/Kconfig" 25 26# architecture-specific options below 27 28choice 29 prompt "Base ISA" 30 default ARCH_RV32I 31 32config ARCH_RV32I 33 bool "RV32I" 34 select 32BIT 35 help 36 Choose this option to target the RV32I base integer instruction set. 37 38config ARCH_RV64I 39 bool "RV64I" 40 select 64BIT 41 select PHYS_64BIT 42 help 43 Choose this option to target the RV64I base integer instruction set. 44 45endchoice 46 47choice 48 prompt "Code Model" 49 default CMODEL_MEDLOW 50 51config CMODEL_MEDLOW 52 bool "medium low code model" 53 help 54 U-Boot and its statically defined symbols must lie within a single 2 GiB 55 address range and must lie between absolute addresses -2 GiB and +2 GiB. 56 57config CMODEL_MEDANY 58 bool "medium any code model" 59 help 60 U-Boot and its statically defined symbols must be within any single 2 GiB 61 address range. 62 63endchoice 64 65choice 66 prompt "Run Mode" 67 default RISCV_MMODE 68 69config RISCV_MMODE 70 bool "Machine" 71 help 72 Choose this option to build U-Boot for RISC-V M-Mode. 73 74config RISCV_SMODE 75 bool "Supervisor" 76 help 77 Choose this option to build U-Boot for RISC-V S-Mode. 78 79endchoice 80 81config RISCV_ISA_C 82 bool "Emit compressed instructions" 83 default y 84 help 85 Adds "C" to the ISA subsets that the toolchain is allowed to emit 86 when building U-Boot, which results in compressed instructions in the 87 U-Boot binary. 88 89config RISCV_ISA_A 90 def_bool y 91 92config 32BIT 93 bool 94 95config 64BIT 96 bool 97 98config SIFIVE_CLINT 99 bool 100 depends on RISCV_MMODE 101 select REGMAP 102 select SYSCON 103 help 104 The SiFive CLINT block holds memory-mapped control and status registers 105 associated with software and timer interrupts. 106 107endmenu 108