1menu "RISC-V architecture" 2 depends on RISCV 3 4config SYS_ARCH 5 default "riscv" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_AX25_AE350 12 bool "Support ax25-ae350" 13 14config TARGET_QEMU_VIRT 15 bool "Support QEMU Virt Board" 16 17endchoice 18 19# board-specific options below 20source "board/AndesTech/ax25-ae350/Kconfig" 21source "board/emulation/qemu-riscv/Kconfig" 22 23# platform-specific options below 24source "arch/riscv/cpu/ax25/Kconfig" 25source "arch/riscv/cpu/qemu/Kconfig" 26 27# architecture-specific options below 28 29choice 30 prompt "Base ISA" 31 default ARCH_RV32I 32 33config ARCH_RV32I 34 bool "RV32I" 35 select 32BIT 36 help 37 Choose this option to target the RV32I base integer instruction set. 38 39config ARCH_RV64I 40 bool "RV64I" 41 select 64BIT 42 select PHYS_64BIT 43 help 44 Choose this option to target the RV64I base integer instruction set. 45 46endchoice 47 48choice 49 prompt "Code Model" 50 default CMODEL_MEDLOW 51 52config CMODEL_MEDLOW 53 bool "medium low code model" 54 help 55 U-Boot and its statically defined symbols must lie within a single 2 GiB 56 address range and must lie between absolute addresses -2 GiB and +2 GiB. 57 58config CMODEL_MEDANY 59 bool "medium any code model" 60 help 61 U-Boot and its statically defined symbols must be within any single 2 GiB 62 address range. 63 64endchoice 65 66choice 67 prompt "Run Mode" 68 default RISCV_MMODE 69 70config RISCV_MMODE 71 bool "Machine" 72 help 73 Choose this option to build U-Boot for RISC-V M-Mode. 74 75config RISCV_SMODE 76 bool "Supervisor" 77 help 78 Choose this option to build U-Boot for RISC-V S-Mode. 79 80endchoice 81 82config RISCV_ISA_C 83 bool "Emit compressed instructions" 84 default y 85 help 86 Adds "C" to the ISA subsets that the toolchain is allowed to emit 87 when building U-Boot, which results in compressed instructions in the 88 U-Boot binary. 89 90config RISCV_ISA_A 91 def_bool y 92 93config 32BIT 94 bool 95 96config 64BIT 97 bool 98 99config SIFIVE_CLINT 100 bool 101 depends on RISCV_MMODE 102 select REGMAP 103 select SYSCON 104 help 105 The SiFive CLINT block holds memory-mapped control and status registers 106 associated with software and timer interrupts. 107 108config RISCV_RDTIME 109 bool 110 default y if RISCV_SMODE 111 help 112 The provides the riscv_get_time() API that is implemented using the 113 standard rdtime instruction. This is the case for S-mode U-Boot, and 114 is useful for processors that support rdtime in M-mode too. 115 116config SYS_MALLOC_F_LEN 117 default 0x1000 118 119endmenu 120