1menu "RISC-V architecture" 2 depends on RISCV 3 4config SYS_ARCH 5 default "riscv" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_AX25_AE350 12 bool "Support ax25-ae350" 13 14config TARGET_QEMU_VIRT 15 bool "Support QEMU Virt Board" 16 17endchoice 18 19# board-specific options below 20source "board/AndesTech/ax25-ae350/Kconfig" 21source "board/emulation/qemu-riscv/Kconfig" 22 23# platform-specific options below 24source "arch/riscv/cpu/ax25/Kconfig" 25 26# architecture-specific options below 27 28choice 29 prompt "Base ISA" 30 default ARCH_RV32I 31 32config ARCH_RV32I 33 bool "RV32I" 34 select 32BIT 35 help 36 Choose this option to target the RV32I base integer instruction set. 37 38config ARCH_RV64I 39 bool "RV64I" 40 select 64BIT 41 select PHYS_64BIT 42 help 43 Choose this option to target the RV64I base integer instruction set. 44 45endchoice 46 47config RISCV_ISA_C 48 bool "Emit compressed instructions" 49 default y 50 help 51 Adds "C" to the ISA subsets that the toolchain is allowed to emit 52 when building U-Boot, which results in compressed instructions in the 53 U-Boot binary. 54 55config RISCV_ISA_A 56 def_bool y 57 58config RISCV_SMODE 59 bool "Run in S-Mode" 60 help 61 Enable this option to build U-Boot for RISC-V S-Mode 62 63config 32BIT 64 bool 65 66config 64BIT 67 bool 68 69endmenu 70