1117a433dSBin Mengmenu "RISC-V architecture" 2f94c44e5SRick Chen depends on RISCV 3f94c44e5SRick Chen 4f94c44e5SRick Chenconfig SYS_ARCH 5f94c44e5SRick Chen default "riscv" 6f94c44e5SRick Chen 7f94c44e5SRick Chenchoice 8f94c44e5SRick Chen prompt "Target select" 9f94c44e5SRick Chen optional 10f94c44e5SRick Chen 116f4dd62fSRick Chenconfig TARGET_AX25_AE350 126f4dd62fSRick Chen bool "Support ax25-ae350" 13f94c44e5SRick Chen 14510e379cSBin Mengconfig TARGET_QEMU_VIRT 15510e379cSBin Meng bool "Support QEMU Virt Board" 16510e379cSBin Meng 17f94c44e5SRick Chenendchoice 18f94c44e5SRick Chen 1952923c6dSRick Chen# board-specific options below 206f4dd62fSRick Chensource "board/AndesTech/ax25-ae350/Kconfig" 21510e379cSBin Mengsource "board/emulation/qemu-riscv/Kconfig" 22f94c44e5SRick Chen 2352923c6dSRick Chen# platform-specific options below 2452923c6dSRick Chensource "arch/riscv/cpu/ax25/Kconfig" 2584304d48SBin Mengsource "arch/riscv/cpu/qemu/Kconfig" 2652923c6dSRick Chen 2752923c6dSRick Chen# architecture-specific options below 2852923c6dSRick Chen 29f94c44e5SRick Chenchoice 30862e2e75SLukas Auer prompt "Base ISA" 31862e2e75SLukas Auer default ARCH_RV32I 32f94c44e5SRick Chen 33862e2e75SLukas Auerconfig ARCH_RV32I 34862e2e75SLukas Auer bool "RV32I" 35f94c44e5SRick Chen select 32BIT 36f94c44e5SRick Chen help 37862e2e75SLukas Auer Choose this option to target the RV32I base integer instruction set. 38f94c44e5SRick Chen 39862e2e75SLukas Auerconfig ARCH_RV64I 40862e2e75SLukas Auer bool "RV64I" 41f94c44e5SRick Chen select 64BIT 4271158564SLukas Auer select PHYS_64BIT 43f94c44e5SRick Chen help 44862e2e75SLukas Auer Choose this option to target the RV64I base integer instruction set. 45f94c44e5SRick Chen 46f94c44e5SRick Chenendchoice 47f94c44e5SRick Chen 488176ea4dSLukas Auerchoice 498176ea4dSLukas Auer prompt "Code Model" 508176ea4dSLukas Auer default CMODEL_MEDLOW 518176ea4dSLukas Auer 528176ea4dSLukas Auerconfig CMODEL_MEDLOW 538176ea4dSLukas Auer bool "medium low code model" 548176ea4dSLukas Auer help 558176ea4dSLukas Auer U-Boot and its statically defined symbols must lie within a single 2 GiB 568176ea4dSLukas Auer address range and must lie between absolute addresses -2 GiB and +2 GiB. 578176ea4dSLukas Auer 588176ea4dSLukas Auerconfig CMODEL_MEDANY 598176ea4dSLukas Auer bool "medium any code model" 608176ea4dSLukas Auer help 618176ea4dSLukas Auer U-Boot and its statically defined symbols must be within any single 2 GiB 628176ea4dSLukas Auer address range. 638176ea4dSLukas Auer 648176ea4dSLukas Auerendchoice 658176ea4dSLukas Auer 663cfc8252SAnup Patelchoice 673cfc8252SAnup Patel prompt "Run Mode" 683cfc8252SAnup Patel default RISCV_MMODE 693cfc8252SAnup Patel 703cfc8252SAnup Patelconfig RISCV_MMODE 713cfc8252SAnup Patel bool "Machine" 723cfc8252SAnup Patel help 733cfc8252SAnup Patel Choose this option to build U-Boot for RISC-V M-Mode. 743cfc8252SAnup Patel 753cfc8252SAnup Patelconfig RISCV_SMODE 763cfc8252SAnup Patel bool "Supervisor" 773cfc8252SAnup Patel help 783cfc8252SAnup Patel Choose this option to build U-Boot for RISC-V S-Mode. 793cfc8252SAnup Patel 803cfc8252SAnup Patelendchoice 813cfc8252SAnup Patel 82d57ffa65SLukas Auerconfig RISCV_ISA_C 83d57ffa65SLukas Auer bool "Emit compressed instructions" 84d57ffa65SLukas Auer default y 85d57ffa65SLukas Auer help 86d57ffa65SLukas Auer Adds "C" to the ISA subsets that the toolchain is allowed to emit 87d57ffa65SLukas Auer when building U-Boot, which results in compressed instructions in the 88d57ffa65SLukas Auer U-Boot binary. 89d57ffa65SLukas Auer 90d57ffa65SLukas Auerconfig RISCV_ISA_A 91d57ffa65SLukas Auer def_bool y 92d57ffa65SLukas Auer 93f94c44e5SRick Chenconfig 32BIT 94f94c44e5SRick Chen bool 95f94c44e5SRick Chen 96f94c44e5SRick Chenconfig 64BIT 97f94c44e5SRick Chen bool 98f94c44e5SRick Chen 99644a3cd7SBin Mengconfig SIFIVE_CLINT 100644a3cd7SBin Meng bool 101644a3cd7SBin Meng depends on RISCV_MMODE 102644a3cd7SBin Meng select REGMAP 103644a3cd7SBin Meng select SYSCON 104644a3cd7SBin Meng help 105644a3cd7SBin Meng The SiFive CLINT block holds memory-mapped control and status registers 106644a3cd7SBin Meng associated with software and timer interrupts. 107644a3cd7SBin Meng 108511107d8SAnup Patelconfig RISCV_RDTIME 109511107d8SAnup Patel bool 110511107d8SAnup Patel default y if RISCV_SMODE 111511107d8SAnup Patel help 112511107d8SAnup Patel The provides the riscv_get_time() API that is implemented using the 113511107d8SAnup Patel standard rdtime instruction. This is the case for S-mode U-Boot, and 114511107d8SAnup Patel is useful for processors that support rdtime in M-mode too. 115511107d8SAnup Patel 116*92b64fefSBin Mengconfig SYS_MALLOC_F_LEN 117*92b64fefSBin Meng default 0x1000 118*92b64fefSBin Meng 119f94c44e5SRick Chenendmenu 120