1117a433dSBin Mengmenu "RISC-V architecture" 2f94c44e5SRick Chen depends on RISCV 3f94c44e5SRick Chen 4f94c44e5SRick Chenconfig SYS_ARCH 5f94c44e5SRick Chen default "riscv" 6f94c44e5SRick Chen 7f94c44e5SRick Chenchoice 8f94c44e5SRick Chen prompt "Target select" 9f94c44e5SRick Chen optional 10f94c44e5SRick Chen 116f4dd62fSRick Chenconfig TARGET_AX25_AE350 126f4dd62fSRick Chen bool "Support ax25-ae350" 13f94c44e5SRick Chen 14510e379cSBin Mengconfig TARGET_QEMU_VIRT 15510e379cSBin Meng bool "Support QEMU Virt Board" 16510e379cSBin Meng 17f94c44e5SRick Chenendchoice 18f94c44e5SRick Chen 1952923c6dSRick Chen# board-specific options below 206f4dd62fSRick Chensource "board/AndesTech/ax25-ae350/Kconfig" 21510e379cSBin Mengsource "board/emulation/qemu-riscv/Kconfig" 22f94c44e5SRick Chen 2352923c6dSRick Chen# platform-specific options below 2452923c6dSRick Chensource "arch/riscv/cpu/ax25/Kconfig" 2552923c6dSRick Chen 2652923c6dSRick Chen# architecture-specific options below 2752923c6dSRick Chen 28f94c44e5SRick Chenchoice 29862e2e75SLukas Auer prompt "Base ISA" 30862e2e75SLukas Auer default ARCH_RV32I 31f94c44e5SRick Chen 32862e2e75SLukas Auerconfig ARCH_RV32I 33862e2e75SLukas Auer bool "RV32I" 34f94c44e5SRick Chen select 32BIT 35f94c44e5SRick Chen help 36862e2e75SLukas Auer Choose this option to target the RV32I base integer instruction set. 37f94c44e5SRick Chen 38862e2e75SLukas Auerconfig ARCH_RV64I 39862e2e75SLukas Auer bool "RV64I" 40f94c44e5SRick Chen select 64BIT 4171158564SLukas Auer select PHYS_64BIT 42f94c44e5SRick Chen help 43862e2e75SLukas Auer Choose this option to target the RV64I base integer instruction set. 44f94c44e5SRick Chen 45f94c44e5SRick Chenendchoice 46f94c44e5SRick Chen 47*8176ea4dSLukas Auerchoice 48*8176ea4dSLukas Auer prompt "Code Model" 49*8176ea4dSLukas Auer default CMODEL_MEDLOW 50*8176ea4dSLukas Auer 51*8176ea4dSLukas Auerconfig CMODEL_MEDLOW 52*8176ea4dSLukas Auer bool "medium low code model" 53*8176ea4dSLukas Auer help 54*8176ea4dSLukas Auer U-Boot and its statically defined symbols must lie within a single 2 GiB 55*8176ea4dSLukas Auer address range and must lie between absolute addresses -2 GiB and +2 GiB. 56*8176ea4dSLukas Auer 57*8176ea4dSLukas Auerconfig CMODEL_MEDANY 58*8176ea4dSLukas Auer bool "medium any code model" 59*8176ea4dSLukas Auer help 60*8176ea4dSLukas Auer U-Boot and its statically defined symbols must be within any single 2 GiB 61*8176ea4dSLukas Auer address range. 62*8176ea4dSLukas Auer 63*8176ea4dSLukas Auerendchoice 64*8176ea4dSLukas Auer 65d57ffa65SLukas Auerconfig RISCV_ISA_C 66d57ffa65SLukas Auer bool "Emit compressed instructions" 67d57ffa65SLukas Auer default y 68d57ffa65SLukas Auer help 69d57ffa65SLukas Auer Adds "C" to the ISA subsets that the toolchain is allowed to emit 70d57ffa65SLukas Auer when building U-Boot, which results in compressed instructions in the 71d57ffa65SLukas Auer U-Boot binary. 72d57ffa65SLukas Auer 73d57ffa65SLukas Auerconfig RISCV_ISA_A 74d57ffa65SLukas Auer def_bool y 75d57ffa65SLukas Auer 76d2db2a8fSAnup Patelconfig RISCV_SMODE 77d2db2a8fSAnup Patel bool "Run in S-Mode" 78d2db2a8fSAnup Patel help 79d2db2a8fSAnup Patel Enable this option to build U-Boot for RISC-V S-Mode 80d2db2a8fSAnup Patel 81f94c44e5SRick Chenconfig 32BIT 82f94c44e5SRick Chen bool 83f94c44e5SRick Chen 84f94c44e5SRick Chenconfig 64BIT 85f94c44e5SRick Chen bool 86f94c44e5SRick Chen 87f94c44e5SRick Chenendmenu 88