1117a433dSBin Mengmenu "RISC-V architecture" 2f94c44e5SRick Chen depends on RISCV 3f94c44e5SRick Chen 4f94c44e5SRick Chenconfig SYS_ARCH 5f94c44e5SRick Chen default "riscv" 6f94c44e5SRick Chen 7f94c44e5SRick Chenchoice 8f94c44e5SRick Chen prompt "Target select" 9f94c44e5SRick Chen optional 10f94c44e5SRick Chen 116f4dd62fSRick Chenconfig TARGET_AX25_AE350 126f4dd62fSRick Chen bool "Support ax25-ae350" 13f94c44e5SRick Chen 14510e379cSBin Mengconfig TARGET_QEMU_VIRT 15510e379cSBin Meng bool "Support QEMU Virt Board" 16510e379cSBin Meng 17f94c44e5SRick Chenendchoice 18f94c44e5SRick Chen 1952923c6dSRick Chen# board-specific options below 206f4dd62fSRick Chensource "board/AndesTech/ax25-ae350/Kconfig" 21510e379cSBin Mengsource "board/emulation/qemu-riscv/Kconfig" 22f94c44e5SRick Chen 2352923c6dSRick Chen# platform-specific options below 2452923c6dSRick Chensource "arch/riscv/cpu/ax25/Kconfig" 2552923c6dSRick Chen 2652923c6dSRick Chen# architecture-specific options below 2752923c6dSRick Chen 28f94c44e5SRick Chenchoice 29862e2e75SLukas Auer prompt "Base ISA" 30862e2e75SLukas Auer default ARCH_RV32I 31f94c44e5SRick Chen 32862e2e75SLukas Auerconfig ARCH_RV32I 33862e2e75SLukas Auer bool "RV32I" 34f94c44e5SRick Chen select 32BIT 35f94c44e5SRick Chen help 36862e2e75SLukas Auer Choose this option to target the RV32I base integer instruction set. 37f94c44e5SRick Chen 38862e2e75SLukas Auerconfig ARCH_RV64I 39862e2e75SLukas Auer bool "RV64I" 40f94c44e5SRick Chen select 64BIT 4171158564SLukas Auer select PHYS_64BIT 42f94c44e5SRick Chen help 43862e2e75SLukas Auer Choose this option to target the RV64I base integer instruction set. 44f94c44e5SRick Chen 45f94c44e5SRick Chenendchoice 46f94c44e5SRick Chen 478176ea4dSLukas Auerchoice 488176ea4dSLukas Auer prompt "Code Model" 498176ea4dSLukas Auer default CMODEL_MEDLOW 508176ea4dSLukas Auer 518176ea4dSLukas Auerconfig CMODEL_MEDLOW 528176ea4dSLukas Auer bool "medium low code model" 538176ea4dSLukas Auer help 548176ea4dSLukas Auer U-Boot and its statically defined symbols must lie within a single 2 GiB 558176ea4dSLukas Auer address range and must lie between absolute addresses -2 GiB and +2 GiB. 568176ea4dSLukas Auer 578176ea4dSLukas Auerconfig CMODEL_MEDANY 588176ea4dSLukas Auer bool "medium any code model" 598176ea4dSLukas Auer help 608176ea4dSLukas Auer U-Boot and its statically defined symbols must be within any single 2 GiB 618176ea4dSLukas Auer address range. 628176ea4dSLukas Auer 638176ea4dSLukas Auerendchoice 648176ea4dSLukas Auer 653cfc8252SAnup Patelchoice 663cfc8252SAnup Patel prompt "Run Mode" 673cfc8252SAnup Patel default RISCV_MMODE 683cfc8252SAnup Patel 693cfc8252SAnup Patelconfig RISCV_MMODE 703cfc8252SAnup Patel bool "Machine" 713cfc8252SAnup Patel help 723cfc8252SAnup Patel Choose this option to build U-Boot for RISC-V M-Mode. 733cfc8252SAnup Patel 743cfc8252SAnup Patelconfig RISCV_SMODE 753cfc8252SAnup Patel bool "Supervisor" 763cfc8252SAnup Patel help 773cfc8252SAnup Patel Choose this option to build U-Boot for RISC-V S-Mode. 783cfc8252SAnup Patel 793cfc8252SAnup Patelendchoice 803cfc8252SAnup Patel 81d57ffa65SLukas Auerconfig RISCV_ISA_C 82d57ffa65SLukas Auer bool "Emit compressed instructions" 83d57ffa65SLukas Auer default y 84d57ffa65SLukas Auer help 85d57ffa65SLukas Auer Adds "C" to the ISA subsets that the toolchain is allowed to emit 86d57ffa65SLukas Auer when building U-Boot, which results in compressed instructions in the 87d57ffa65SLukas Auer U-Boot binary. 88d57ffa65SLukas Auer 89d57ffa65SLukas Auerconfig RISCV_ISA_A 90d57ffa65SLukas Auer def_bool y 91d57ffa65SLukas Auer 92f94c44e5SRick Chenconfig 32BIT 93f94c44e5SRick Chen bool 94f94c44e5SRick Chen 95f94c44e5SRick Chenconfig 64BIT 96f94c44e5SRick Chen bool 97f94c44e5SRick Chen 98*644a3cd7SBin Mengconfig SIFIVE_CLINT 99*644a3cd7SBin Meng bool 100*644a3cd7SBin Meng depends on RISCV_MMODE 101*644a3cd7SBin Meng select REGMAP 102*644a3cd7SBin Meng select SYSCON 103*644a3cd7SBin Meng help 104*644a3cd7SBin Meng The SiFive CLINT block holds memory-mapped control and status registers 105*644a3cd7SBin Meng associated with software and timer interrupts. 106*644a3cd7SBin Meng 107f94c44e5SRick Chenendmenu 108