1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#include <config.h> 11#include <ppc_asm.tmpl> 12#include <ppc_defs.h> 13 14#include <asm/cache.h> 15 16/*------------------------------------------------------------------------------- */ 17/* Function: ppcDcbf */ 18/* Description: Data Cache block flush */ 19/* Input: r3 = effective address */ 20/* Output: none. */ 21/*------------------------------------------------------------------------------- */ 22 .globl ppcDcbf 23ppcDcbf: 24 dcbf r0,r3 25 blr 26 27/*------------------------------------------------------------------------------- */ 28/* Function: ppcDcbi */ 29/* Description: Data Cache block Invalidate */ 30/* Input: r3 = effective address */ 31/* Output: none. */ 32/*------------------------------------------------------------------------------- */ 33 .globl ppcDcbi 34ppcDcbi: 35 dcbi r0,r3 36 blr 37 38/*-------------------------------------------------------------------------- 39 * Function: ppcDcbz 40 * Description: Data Cache block zero. 41 * Input: r3 = effective address 42 * Output: none. 43 *-------------------------------------------------------------------------- */ 44 45 .globl ppcDcbz 46ppcDcbz: 47 dcbz r0,r3 48 blr 49 50/*------------------------------------------------------------------------------- */ 51/* Function: ppcSync */ 52/* Description: Processor Synchronize */ 53/* Input: none. */ 54/* Output: none. */ 55/*------------------------------------------------------------------------------- */ 56 .globl ppcSync 57ppcSync: 58 sync 59 blr 60 61/* 62 * Write any modified data cache blocks out to memory and invalidate them. 63 * Does not invalidate the corresponding instruction cache blocks. 64 * 65 * flush_dcache_range(unsigned long start, unsigned long stop) 66 */ 67_GLOBAL(flush_dcache_range) 68#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) 69 li r5,L1_CACHE_BYTES-1 70 andc r3,r3,r5 71 subf r4,r3,r4 72 add r4,r4,r5 73 srwi. r4,r4,L1_CACHE_SHIFT 74 beqlr 75 mtctr r4 76 771: dcbf 0,r3 78 addi r3,r3,L1_CACHE_BYTES 79 bdnz 1b 80 sync /* wait for dcbst's to get to ram */ 81#endif 82 blr 83 84/* 85 * Like above, but invalidate the D-cache. This is used by the 8xx 86 * to invalidate the cache so the PPC core doesn't get stale data 87 * from the CPM (no cache snooping here :-). 88 * 89 * invalidate_dcache_range(unsigned long start, unsigned long stop) 90 */ 91_GLOBAL(invalidate_dcache_range) 92#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) 93 li r5,L1_CACHE_BYTES-1 94 andc r3,r3,r5 95 subf r4,r3,r4 96 add r4,r4,r5 97 srwi. r4,r4,L1_CACHE_SHIFT 98 beqlr 99 mtctr r4 100 101 sync 1021: dcbi 0,r3 103 addi r3,r3,L1_CACHE_BYTES 104 bdnz 1b 105 sync /* wait for dcbi's to get to ram */ 106#endif 107 blr 108 109